Forum: GNU Radio Recompiling FPGA with Quartus 6.1 tool

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0eaa339f1c4bc8cf1606915c7f6d61cb?d=identicon&s=25 Jim Murashige (Guest)
on 2007-01-06 19:30
(Received via mailing list)
I was trying to recompile the usrp_std.v just to try out the tools,
since we plan to

make future changes to the FPGA.  However only Quartus II v6.1 is
available on

the Altera website.  It compiles and synthesizes fine, but it ends up
with

15501 blocks of type logic cell which just won't fit into the 12060
block EP1C12Q240C8N.

Is there a compile setting that needs to be set or something edited in
the source

to get the logic cell size down so it will fit into the USRP FPGA?



Thanks

Jim Murashige, Rosum
745d8202ef5a58c1058d0e5395a78f9c?d=identicon&s=25 Eric Blossom (Guest)
on 2007-01-06 19:31
(Received via mailing list)
On Fri, Jan 05, 2007 at 06:36:42PM -0800, Jim Murashige wrote:
> block EP1C12Q240C8N.
> Jim Murashige, Rosum
Hi Jim,

This is news to me.  Did you use our project file?  If so, this sounds
like a regression in Quartus.  Last time I built everything I used
Quartus 6.0sp1.  I suggest sending email to somebody at Altera and
asking for a link to the earlier version.

Eric
3596cfe1d579c65b9babd35e8787977c?d=identicon&s=25 Matt Ettus (Guest)
on 2007-01-06 22:33
(Received via mailing list)
Jim Murashige wrote:
> block EP1C12Q240C8N.
>
> Is there a compile setting that needs to be set or something edited in
> the source
>
> to get the logic cell size down so it will fit into the USRP FPGA?
>

I had no problem with nuilding a freshly-checked out version on Quartus
6.1. It came to 11,100 logic elements, 92% full.

Matt
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