I was trying to recompile the usrp_std.v just to try out the tools,
since we plan to
make future changes to the FPGA. However only Quartus II v6.1 is
the Altera website. It compiles and synthesizes fine, but it ends up
15501 blocks of type logic cell which just won’t fit into the 12060
Is there a compile setting that needs to be set or something edited in
to get the logic cell size down so it will fit into the USRP FPGA?
Jim Murashige, Rosum