Forum: GNU Radio usrp2 tune two different frequencies

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7de99ba7a8144e8f34524dc0ca683bd7?d=identicon&s=25 unknown (Guest)
on 2009-04-20 16:35
(Received via mailing list)
Hi all-

is it possible to tune the USRP2 to two different frequencies?  I can do
this with the USRP1 and a LFRX daughterboard using usrp.tune twice:

# Ch 0
r = usrp.tune(self.u, 0, self.subdev[0], target_freq1)

# Ch 1
r = usrp.tune(self.u, 1, self.subdev[1], target_freq2)

to tune each DDC to a separate frequency.  However, it's not clear to me
how to do this with the USRP2 since in the examples I saw there is no
explicit mention of which subdevice is being tuned:

r = self.u.set_center_freq(target_freq1)

thanks for any suggestions.

eric
D0072e69d706bb3ca211d33a1b536e2c?d=identicon&s=25 Johnathan Corgan (Guest)
on 2009-04-20 16:59
(Received via mailing list)
On Mon, Apr 20, 2009 at 7:33 AM,  <ematlis@nd.edu> wrote:

> is it possible to tune the USRP2 to two different frequencies?  I can do
> this with the USRP1 and a LFRX daughterboard using usrp.tune twice:

The USRP has one receive daughterboard and one baseband DDC, so no,
you can only tune to one center frequency.

However, if your signals of interest are close enough, you can set the
center frequency to the mid-point between them, set the decimation
rate to that which would give you a frequency band that contains both
signals, then separate them on the host inside your GNU Radio
flowgraph using two DDC blocks.

Johnathan
7de99ba7a8144e8f34524dc0ca683bd7?d=identicon&s=25 unknown (Guest)
on 2009-04-20 17:02
(Received via mailing list)
On Mon, 20 Apr 2009, Johnathan Corgan wrote:

> rate to that which would give you a frequency band that contains both
> signals, then separate them on the host inside your GNU Radio
> flowgraph using two DDC blocks.
>
> Johnathan
>
I see, thanks for the help.

eric
D0072e69d706bb3ca211d33a1b536e2c?d=identicon&s=25 Johnathan Corgan (Guest)
on 2009-04-20 17:06
(Received via mailing list)
On Mon, Apr 20, 2009 at 7:44 AM, Johnathan Corgan
<jcorgan@corganenterprises.com> wrote:

> The USRP has one receive daughterboard and one baseband DDC, so no,
> you can only tune to one center frequency.

I of course meant the USRP2 here.

Johnathan
7de99ba7a8144e8f34524dc0ca683bd7?d=identicon&s=25 unknown (Guest)
on 2009-04-20 17:10
(Received via mailing list)
On Mon, 20 Apr 2009, Johnathan Corgan wrote:

> On Mon, Apr 20, 2009 at 7:44 AM, Johnathan Corgan
> <jcorgan@corganenterprises.com> wrote:
>
>> The USRP has one receive daughterboard and one baseband DDC, so no,
>> you can only tune to one center frequency.
>
> I of course meant the USRP2 here.
>
> Johnathan
>
Is there any reason why the situation could not be the same as with the
USPR1, with which I can program 2 DDC's on 1 LFRX daughterboard (with
the
appropriate mux) to tune in two separate frequencies?

thanks,
eric
D0072e69d706bb3ca211d33a1b536e2c?d=identicon&s=25 Johnathan Corgan (Guest)
on 2009-04-20 17:17
(Received via mailing list)
On Mon, Apr 20, 2009 at 7:59 AM,  <ematlis@nd.edu> wrote:

> Is there any reason why the situation could not be the same as with the
> USPR1, with which I can program 2 DDC's on 1 LFRX daughterboard (with the
> appropriate mux) to tune in two separate frequencies?

Yes, the USRP2 only has one DDC in the FPGA code.

Johnathan
7de99ba7a8144e8f34524dc0ca683bd7?d=identicon&s=25 unknown (Guest)
on 2009-04-20 17:42
(Received via mailing list)
On Mon, 20 Apr 2009, Johnathan Corgan wrote:

> On Mon, Apr 20, 2009 at 7:59 AM,  <ematlis@nd.edu> wrote:
>
>> Is there any reason why the situation could not be the same as with the
>> USPR1, with which I can program 2 DDC's on 1 LFRX daughterboard (with the
>> appropriate mux) to tune in two separate frequencies?
>
> Yes, the USRP2 only has one DDC in the FPGA code.
>
> Johnathan
>
I guess I was just curious why there is only one DDC in the FPGA, and if
it's possible in future that more than one will be made available.

thanks,
eric
74a5f0d4e1615193d25815690cacc5bc?d=identicon&s=25 Gregory Maxwell (Guest)
on 2009-04-20 17:49
(Received via mailing list)
On Mon, Apr 20, 2009 at 11:32 AM,  <ematlis@nd.edu> wrote:
>> Johnathan
>>
> I guess I was just curious why there is only one DDC in the FPGA, and if
> it's possible in future that more than one will be made available.

…especially since the ADC can capture a much larger window than you
will likely want to send to your host.
3596cfe1d579c65b9babd35e8787977c?d=identicon&s=25 Matt Ettus (Guest)
on 2009-04-20 18:39
(Received via mailing list)
ematlis@nd.edu wrote:
>>
>> Johnathan
>>
> I guess I was just curious why there is only one DDC in the FPGA, and if
> it's possible in future that more than one will be made available.


It wouldn't be hard at all to put a second one in there, along with a
second DUC.  Everything is set up to hold it, and there is enough space.

We just haven't had a need yet, since the USRP2 only holds one
daughterboard.  If, however, you want to RX or transmit 2 different
signals on the same daughterboard, or are using a BasicRX/TX with dual
independent real signals at IF, then it would make sense.

Matt
745d8202ef5a58c1058d0e5395a78f9c?d=identicon&s=25 Eric Blossom (Guest)
on 2009-04-20 18:43
(Received via mailing list)
On Mon, Apr 20, 2009 at 11:32:42AM -0400, ematlis@nd.edu wrote:
>> Johnathan
>>
> I guess I was just curious why there is only one DDC in the FPGA, and if
> it's possible in future that more than one will be made available.
>
> thanks,
> eric

Eric, this will probably all change as part of the VRT (VITA-49 work).
A big part of that design work is a strategy for naming all of the
things that you might want to control, and how they're arranged.  For
example, on the USRP1 you have up to 4 DDCs, but they are all run at
the same decimation rate.

The current working concept is that we'll have a hierarchy something
like this:

  Physical Unit (e.g., mimo interconnected USRP2s)
    Pipeline (everthing in the pipeline is running at the same sample
rate)
      Signal (would handle multiple DDCs in a given pipeline)

We'd like to come up with a control protocol that gives us reasonable
flexibility.  That is, users can build custom FPGA images without
having to hack up a bunch of host and/or firmware to make the new FPGA
image work.  Our current on-the-wire protocol is quite fragile.  It
was originally cooked up to facilitate quick testing of the USRP2, but
then the USRP2's shipped with it...  The VRT work will be much better
thought out, and will support ease of use, flexibility, and
extensibility.

Eric
7de99ba7a8144e8f34524dc0ca683bd7?d=identicon&s=25 unknown (Guest)
on 2009-04-20 18:47
(Received via mailing list)
On Mon, 20 Apr 2009, Matt Ettus wrote:

>>> Yes, the USRP2 only has one DDC in the FPGA code.
> We just haven't had a need yet, since the USRP2 only holds one
> daughterboard.  If, however, you want to RX or transmit 2 different
> signals on the same daughterboard, or are using a BasicRX/TX with dual
> independent real signals at IF, then it would make sense.
>
> Matt
>
I'm in a position only to say, yes please!  I do actually use the
BasicRX/LFRX daughterboards with 2 real channels.

thanks,
eric
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