On Mon, Apr 20, 2009 at 11:32:42AM -0400, [email protected] wrote:
I guess I was just curious why there is only one DDC in the FPGA, and if
it’s possible in future that more than one will be made available.
Eric, this will probably all change as part of the VRT (VITA-49 work).
A big part of that design work is a strategy for naming all of the
things that you might want to control, and how they’re arranged. For
example, on the USRP1 you have up to 4 DDCs, but they are all run at
the same decimation rate.
The current working concept is that we’ll have a hierarchy something
Physical Unit (e.g., mimo interconnected USRP2s)
Pipeline (everthing in the pipeline is running at the same sample
Signal (would handle multiple DDCs in a given pipeline)
We’d like to come up with a control protocol that gives us reasonable
flexibility. That is, users can build custom FPGA images without
having to hack up a bunch of host and/or firmware to make the new FPGA
image work. Our current on-the-wire protocol is quite fragile. It
was originally cooked up to facilitate quick testing of the USRP2, but
then the USRP2’s shipped with it… The VRT work will be much better
thought out, and will support ease of use, flexibility, and