Where is the signal of incoming sample in FPGA?

Hi, All,

We wrote codes for FFT in FPGA. In our codes, we start FFT when we get a
START signal.
Where can we connect this signal? How do we know that samples are
incoming?
There are lots of signals in u1e.v that look like having this function,
such as input FPGA_RXD, input fpga_rxd1, input db_miso_rx.
If there exists such a signal, is it a pulse or a constant high value
when
FPGA is reading data from ADC?
Basically, where can we see the codes that FPGA notifies the host to
read
data from the FPGA?

Also, the ADC gives 12 bits representation, additions in FFT may change
the
values to 13 bits.
We believe that the original codes are designed to read samples as
12bits
from FPGA to host.
Where is this part?
We are considering reducing 13bits to 12bits or reading samples as
13bits.

Thanks,
Yooxi

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