VHDL help!

Hi List,
I’m trying to realize a 1 bit quantizer on the FPGA, but I’ve some
problem to understand how VHDL works!

So, I hope you can help me.
In the file /usrp/fpga/sdr_lib/rx_buffer.v there are two wire:

wire [4:0] bitwidth;
wire [3:0] bitshift;

What’s the function of these?

Davide A.

web: http://www.davideanastasia.com/
email: [email protected]

On Monday 05 February 2007 20:20, Davide A. wrote:

I’m trying to realize a 1 bit quantizer on the FPGA, but I’ve some
problem to understand how VHDL works!

So, I hope you can help me.
In the file /usrp/fpga/sdr_lib/rx_buffer.v there are two wire:

wire [4:0] bitwidth;
wire [3:0] bitshift;

What’s the function of these?

This is Verilog not VHDL…

They declare wire buses you can use to connect things together with.

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