I’m going to implement standalone development platform using USRP2 board
and xilinx virtex5 board. I plan to put PHY on USRP2 board while MAC and
Application implementation would be on virtex5 board, and these two
boards would be connected through GPIO.
Basically I’m going to attach PHY’s verilog to USRP2’s existing verilog.
May i know anyone has done similar project before? Can someone point me
out where should i start to understand USRP2’s verilog (since i could
not find any relevant doc, describing the architecture of verilog code)?