Usrp2 master clock modifications

Hi,

I tought I’d share some experiences with running the usrp2 system
clock with something else than 100 MHz (so I can google it when I
forget).

Matt suggested that I could remove the 100 MHz oscillator and input my
own external clock instead. The VCTCXO was easy to remove, and I put a
1 Vpp sample clock in the place of pin 3. Another option would have
been to buy a VCTCXO with another frequency, but I just thought this
would be more straightforward.

I also modified the following places:

firmware/microblaze/lib/memory_map.h:#define MASTER_CLK_RATE 100000000
firmware/microblaze/divisors.py:master_clk = 100e6
lib/usrp/usrp2/usrp2_iface.cpp: double get_master_clock_freq(void){

and flashed the firmware after compiling.

I initially tried with a 60 MHz clock. The, but I couldn’t get the
sampling to start. I then tried 80 MHz with better success. The seems
to work ok, but I’m still in the process of verifying it.

juha

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