USRP2, is that possible to skip the Ethernet and pass data through general purpose (physically acces

Hi,

I am using USRP2+RFX2400 board and trying to adapt our packetized
communication on the board. As I understand the Ethernet does its own
packetization on information data and we don’t like that. therefore we
are looking into avoid passing our information data to the board through
Ethernet. We are also fine to make the configuration values for other
peripherals on the board (such as DAC, ADC and daughter boards) fixed so
that we still can get away with no Ethernet interface. so we are
interested to know if there is a general purpose input bus (at least 5
pins) that I can use to pass my data serially to the FPGA. That means I
would like to see if it is possible to remove all the Verilog codes in
FPGA related to handling the Ethernet interface and get the data I’d
like to process through a general purpose input bus (at least 5 pins for
clock and serial data input and 3 handshaking signals) instead of
Ethernet port. For that reason, I need this general purpose bus to be
physically accessible on the board so that I can connect them to a
digital signal generator. Do you have any suggestion/recommendation for
me?

Thanks,
Malihe

Malihe,

The USRP2 drivers are designed to abstract the user from the device
transport, and in normal use you shouldn’t have to concern yourself with
the transport layer at all. You provide a stream of data in gnuradio,
and the USRP2 provides a stream of data out the device (or vice versa).
All the magic that happens between should be transparent. To the user,
there is no packetization at all on transmitted data – discrete
Ethernet data packets are buffered in the USRP2 and transmitted
seamlessly by the device.

If you are seeing “gaps” in signal when viewed on a scope, you are
probably experiencing buffer underruns caused by running at a data rate
too fast for your CPU to handle.

Can you explain the problem you are seeing with your device?

Nick

On Wed, Sep 01, 2010 at 07:07:26PM -0600, Malihe A. wrote:

is a general purpose input bus (at least 5 pins) that I can use to
pass my data serially to the FPGA.

The MICTOR debug connector, J301, has 32 uncommitted pins and 2 clks.
It’s currently configured as an output, but you can use it for whatever
you like. Look in u2_rev3.v and/or u2_core.v.

output [31:0] debug,
output [1:0] debug_clk,

Thanks,
Malihe

Eric

Hi Nick,
Actually we are using the USRP2 not for a SDR application, but we are
using it to test our physical layer asynchronous backet based
communication. For that I have to change the FPGA code and remove the
interpolation/decimation and replace it with a spreading scheme. for
that I need to know exactly what is the nature of data I am receiving at
the FPGA and what is its maximum rate or forget about Ethernet and get a
separate bus for me to pass the data to the FPGA .
Assuming I want to use Ethernet, let’s say I want to send the stream
‘0100001’, and I pick DBPSK as the modulation. can you please explain
what is the relation of the DBPSK modulated data and “GMII_RXD” input to
the FPGA or “sample” input to the dsp_core_tx? is that FPGA receives 8
bits per symbol sent over Ethernet?
Also, do you have a ready to use Python code for USRP2 device which
generates for example a SIN wave at the transmitter and captures it at
the receives?

Thanks,
Malihe

Hi Eric, thanks for the insightful reply. I will be using these pins for
my design. what else is provided to the board through Ethernet? If I
understand correct, the configuration data for DAC (such as the IF
frequency, etc) is provided through Ethernet, but we don’t really want
to change those, so I’d like to program those registers one and won’t
touch them again. For that do I need to just change the firmware? Is
there any other important point I need to care about if I remove the
Ethernet modules in FPGA?

Thanks,
Malihe

Hi Nick,
Actually we are using the USRP2 not for a SDR application, but we are
using it to test our physical layer asynchronous backet based
communication. For that I have to change the FPGA code and remove the
interpolation/decimation and replace it with a spreading scheme. for
that I need to know exactly what is the nature of data I am receiving at
the FPGA and what is its maximum rate or forget about Ethernet and get a
separate bus for me to pass the data to the FPGA .
Assuming I want to use Ethernet, let’s say I want to send the stream
‘0100001’, and I pick DBPSK as the modulation. can you please explain
what is the relation of the DBPSK modulated data and “GMII_RXD” input to
the FPGA or “sample” input to the dsp_core_tx? is that FPGA receives 8
bits per symbol sent over Ethernet?
Also, do you have a ready to use Python code for USRP2 device which
generates for example a SIN wave at the transmitter and captures it at
the receives?

Thanks,
Malihe

Malihe,

Date: Thu, 2 Sep 2010 14:19:54 -0600
From: [email protected]

Actually we are using the USRP2 not for a SDR application, but we are
using it to test our physical layer asynchronous backet based
communication. For that I have to change the FPGA code and remove the
interpolation/decimation and replace it with a spreading scheme.

Assuming your spreading doesn’t bring your bandwidth over around 25MHz,
you should be able to do the spreading operation on the host and
transmit the spread baseband data to the USRP2 via Gnuradio. The host
typically does not send unmodulated data to the USRP2; the host side,
usually using Gnuradio, performs the desired DSP operations on your raw
information such as spreading, shaping, and modulating, and sends the
resulting complex waveform to the USRP2 as raw 16-bit samples. The USRP2
itself knows nothing about your original unmodulated data.

for
that I need to know exactly what is the nature of data I am receiving at
the FPGA and what is its maximum rate or forget about Ethernet and get a
separate bus for me to pass the data to the FPGA .

The data you are receiving at the FPGA is whatever you send to it – the
interpolation rate you pick determines the sample rate the USRP2 will
run at. The interpolator will handle upsampling the raw samples to match
the data rate the DACs run at. It’s up to you (using Gnuradio) to encode
your data into an appropriate waveform for your application.

Assuming I want to use Ethernet, let’s say I want to send the stream
‘0100001’, and I pick DBPSK as the modulation. can you please explain
what is the relation of the DBPSK modulated data and “GMII_RXD” input to
the FPGA or “sample” input to the dsp_core_tx? is that FPGA receives 8
bits per symbol sent over Ethernet?

Whatever raw samples you send into gnuradio get sent to the FPGA (I’m
simplifying here: see the link below for details). The USRP2 itself does
not know or care that you are using DBPSK or that you are sending
‘0100001’. It sounds like you might have a misconception of exactly what
the USRP2 is doing. This FAQ is for the USRP1, but the overall
description applies also to the USRP2:
http://gnuradio.org/redmine/wiki/gnuradio/UsrpFAQ

Also, do you have a ready to use Python code for USRP2 device which
generates for example a SIN wave at the transmitter and captures it at
the receives?

A simple GRC flowgraph would perform this function for you. You can use
a signal source to feed a USRP2 sink, and then a USRP2 source to feed an
FFT sink (or whatever sink you like). The parameters for these blocks
depend on what daughterboards you are using for TX and RX and whether
you are using the UHD driver or not.

Nick

Malihe,

Your understanding is basically correct. I misunderstood your request –
I didn’t realize you had an existing FPGA design you were integrating
with the USRP2, and figured you were going about things the hard way.

Nothing happens to Ethernet packets between the host transmission and
GMII_TX – the USRP2 MAC receives the same data that goes out the host
MAC. I was trying to say that modulation is typically done in Gnuradio,
not in the FPGA, and so data on the wire is typically baseband modulated
and not a data bitstream. If you are implementing the modulation in FPGA
you are of course free to define the data on the wire however you like.

For your purposes you should be able to take your data straight from the
MAC and buffer and encode it in whatever way you see fit.

Nick


Hi Nick,

I think I should explain my project better. We are developing a physical
layer protocol for an asynchronous packet based transceiver all in
Verilog. The design has been simulated so far using ModelSim. The target
of the project is the VLSI fabrication of this design. Thus all the
signal processing (digital modulation (for now we are interested in BPSK
digital modulation), packetization, spreading, filtering ) has to be
done in FPGA, and it should be as stand alone as possible. The reason we
picked USRP2 was that it was a compact board with RF specification quite
close to our requirements. Our understanding was that we can get one
computer (host) to transmit stream of bits to the USRP2, do the
processing in FPGA and send the data over air, and the second USRP2
would capture the signal and again FPGA would do the processing and
eventually pass the data (through Ethernet) to the second host
(computer). I thought, if I generate a stream of bits in the first host
(TX) and do BPSK modulation and pass them to the USRP2 using Gnuradio,
the two 16 bit I and Q port that I get at the DSP core of the FPGA are
two bytes of that stream of bits and now I can continue with
packetization and the rest of my processing inside FPGA (basically
replacing the interpolation module with my spreading module) and redo
that process at the receiver to retrieve the generated bit stream.
I have already read through the DSP codes inside the FPGA. What I
understand from your email below was that I can’t retrieve the bit
stream (generated at the host) in the FPGA and the 16 bits I and Q are
modulated, shaped sample representation of the bit stream. This is a bit
confusing for me because I thought (assuming the host just generates the
bits and does the BPSK modulation) the Ethernet decoder (DP83865) of the
USRP2 is basically compensating (undo-ing) the processing that was
performed on the bits (by Ethernet encoder) right before they leave the
host (computer) so that the Ethernet becomes transparent. If that is not
the case, my only solution is to pass the bit stream to the FPGA using
the debug port!
Would you please let me know which part of my assumption is wrong?

Thanks,
Malihe

I have changed the FPGA code and I have built the bit file for it. I
would like to keep the same firmware but just change the FPGA code. What
should I do now?

Thanks,
Malihe

Malihe,

Use the USRP2 card burner utility, located in the UHD host code as
host/utils/usrp2_card_burner_gui.py. It is also installed
to /usr/local/share/uhd/utils/ by default. You may have to run the
program as root.

If you only specify an FPGA image when you run the program, the firmware
image will not be overwritten.

Nick

Hi Malihe,

Basically i’m also doing the stand alone system with USRP2 board. We are
going to implement Zigbee PHY + MAC inside fpga. PHY will be inside
USRP2 (Spartan3) while MAC will be on another Xilinx Virtex5 board. And
these two boards will be connected together.

I’m just wondering, it will be useful if we can discuss our development
progress here since we both are modifying existing USRP2 fpga code.
Please let me know what do you think.

Cheers,
Phone Naing

Malihe A. wrote:

Hi Nick,

I think I should explain my project better. We are developing a physical
layer protocol for an asynchronous packet based transceiver all in
Verilog. The design has been simulated so far using ModelSim. The target
of the project is the VLSI fabrication of this design. Thus all the
signal processing (digital modulation (for now we are interested in BPSK
digital modulation), packetization, spreading, filtering ) has to be
done in FPGA, and it should be as stand alone as possible. The reason we
picked USRP2 was that it was a compact board with RF specification quite
close to our requirements. Our understanding was that we can get one
computer (host) to transmit stream of bits to the USRP2, do the
processing in FPGA and send the data over air, and the second USRP2
would capture the signal and again FPGA would do the processing and
eventually pass the data (through Ethernet) to the second host
(computer). I thought, if I generate a stream of bits in the first host
(TX) and do BPSK modulation and pass them to the USRP2 using Gnuradio,
the two 16 bit I and Q port that I get at the DSP core of the FPGA are
two bytes of that stream of bits and now I can continue with
packetization and the rest of my processing inside FPGA (basically
replacing the interpolation module with my spreading module) and redo
that process at the receiver to retrieve the generated bit stream.
I have already read through the DSP codes inside the FPGA. What I
understand from your email below was that I can’t retrieve the bit
stream (generated at the host) in the FPGA and the 16 bits I and Q are
modulated, shaped sample representation of the bit stream. This is a bit
confusing for me because I thought (assuming the host just generates the
bits and does the BPSK modulation) the Ethernet decoder (DP83865) of the
USRP2 is basically compensating (undo-ing) the processing that was
performed on the bits (by Ethernet encoder) right before they leave the
host (computer) so that the Ethernet becomes transparent. If that is not
the case, my only solution is to pass the bit stream to the FPGA using
the debug port!
Would you please let me know which part of my assumption is wrong?

Thanks,
Malihe

Dear Malihe,

We have to burn .bin file SD card. I have also rebuild fpga image by
using ISE 12.1 (in window environment) and use RawEthernet firmware
downloaded from Ettus website.

But with rebuild fpga image and downloaded firmware, i dnt manage to
configure USRP2. Do u able to do it?

PN

Malihe A. wrote:

Hi Nick,
by FPGA image do you mean the .bit file? Thanks,
Malihe

Hi Nick,

I have a USRP2 + RFX2400 which I’d like to use as a transceiver. here
are my questions:
1- Assuming I get two antennas, one connected to TX/RX port and the
second one connected to RX2 port, Can I get the first antenna to act as
the TX (driven only by DAC) and the second one act as RX (driving only
ADC)? If so, do I get 30MHz of bandwidth on each antenna?
2- Is that true that if I don’t configure the DAC, it will use its
default values for example for the modulation, upsampling factor, …?
3- I understand the default modulation of DAC is “NONE”, what is the
default interpolation rate (none, 1x, 2x or 4x)?
4- Assuming I configure the DAC IF frequency to be 0 (modulation
=“NONE”), does that mean if I pick the RF center frequency of the TX and
RX
to be the same, I need no demodulation (to be implemented inside FPGA
)on the data captured from ADC and this data is all baseband?
5- At the TX side, does the dac_a carry interleaved I/Q? or dac_a
carries only I and dac_b carries only Q of the same samples?
6- At the RX side, does the adc_a carry interleaved I/Q? or adc_a
carries only I and adc_b carries only Q of the same samples?

Thanks,
Malihe

Hi Nick,
by FPGA image do you mean the .bit file? Thanks,
Malihe

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