USRP2 FPGA now builds on ISE12

The USRP2 FPGA image can now be built with ISE 12.x. ISE 11.x probably
also works, but since 12 is a free upgrade from 11, I suggest you use
12. Everything still works on ISE 10.1.03 as well.

One additional change is that both the plain (Raw Ethernet) and UDP
versions (for UHD) are in the same tree now. Build the plain version
with:

make bin

in the usrp2/top/u2_rev3 directory, and the UDP version can be built
with:

make -f Makefile.udp bin

This experimental branch is called ise12_exp and you can get it from our
git repository:

http://code.ettus.com/redmine/ettus/projects/show/fpga

It does not quite meet timing yet, but it is plenty good for
experimental work. We will be working on timing closure in the next
couple of weeks. Any feedback would be much appreciated.

Huge thanks go to Ian B. for his help in this porting effort.

Thanks,
Matt

Hi,

I’m currently working on a project using the ucla ZigBee Phy
implementation for the gnuradio framework.
I need some help how to use boost python and smart pointers to manage
a shared memory block from both sides, the python and the c++ side.
It would be great if I could manipulate as little as possible on the c++
side.

The goal is, to be able to write to the memory block from the python
side and read from it from the c++ side.

Is there anyone here who is familiar with boost-python who might be
kind enough to help me!? That would be highly appreciated!

Thank you very much for your help
best regards,
Björn

On Wed, Jun 02, 2010 at 09:32:34AM +0200, [email protected] wrote:

side and read from it from the c++ side.

Is there anyone here who is familiar with boost-python who might be
kind enough to help me!? That would be highly appreciated!

Thank you very much for your help
best regards,
Björn

Björn, given that GNU Radio uses SWIG to glue python and C++
together, I’d advise figuring out how to get it done using SWIG rather
than trying to get boost-python and SWIG to play together nicely.
Nice docs here: http://www.swig.org/doc.html

How do you plan to coordinate access between the C++ and Python sides?
(If the C++ is in a GNU Radio block, it’ll be running in its own
thread…)

Eric

Hello,

Have you tried the new Xilinx’s FIFOs ?

All constraints were met after regenerating the FIFOs using Fifo
Generator
6.1.

I used ise12 branch and compiled the raw ethernet code.

2010/6/1 Matt E. [email protected]