Is there any example python code showing the usage of external clock
and pps inputs of USRP2
Thank you in advance
-Burak
On 04/11/2011 02:35 PM, Burak TUYSUZ wrote:
Is there any example python code showing the usage of external clock
and pps inputs of USRP2
Thank you in advance
-Burak
A good python example would be code generated by grc when you setup the
“ref clock” and “sync” parameters in the uhd usrp source/sink blocks.
http://code.ettus.com/redmine/ettus/projects/uhd/wiki#Gnuradio-UHD
-Josh
Hi Josh,
Is it possible to trigger storing data with pps using GRC I could nor
find a related email.
If so should that be included in FPGA or in software. A related work
would be great
Thanks in advance.
-Burak
On Mon, Apr 11, 2011 at 9:43 PM, Josh B. [email protected] wrote:
“ref clock” and “sync” parameters in the uhd usrp source/sink blocks.
http://code.ettus.com/redmine/ettus/projects/uhd/wiki#Gnuradio-UHD
-Josh
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Burak TUYSUZ
Ph.D. Candidate, Research Assistant
The Pennsylvania State University
Electrical Engineering
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On 04/12/2011 06:06 PM, Burak TUYSUZ wrote:
Hi Josh,
Is it possible to trigger storing data with pps using GRC I could nor
find a related email.
Not from GRC
If so should that be included in FPGA or in software. A related work
would be great
The rx_timed_samples.cpp example in uhd shows how to request samples at
a specific time.
-Josh
On 04/13/2011 11:31 AM, Burak TUYSUZ wrote:
It does not say if it is the falling edge or the rising edge of the
pps. Is it possible to specify that or is it defined?
The convenience function sets the positive edge which seems to be every
device out there.
For advanced configuration, see the c++ doxygen, so you can extrapolate
what the equivalent code in python should be.
http://www.ettus.com/uhd_docs/doxygen/html/structuhd_1_1clock__config__t.html
-Josh
It does not say if it is the falling edge or the rising edge of the
pps. Is it possible to specify that or is it defined?
On 04/13/2011 11:31 AM, Burak TUYSUZ wrote:
It does not say if it is the falling edge or the rising edge of the
pps. Is it possible to specify that or is it defined?
The PPS is always recognized on the rising edge of PPS. To change
this you would need to change the FPGA. The change would be trivial,
but I don’t think that’s what you’d want, since the rising edge is
essentially a universal standard.
The setting which Josh mentions allows you to choose whether PPS is
sampled on the rising or falling edge of the clock. This is important
because there are varying phase differences between the PPS and 10 MHz.
You should connect your source and see which way works better for your
particular source.
Matt
In UHD for the time stamps you suggested to use the cpp interface which
is
fine and there is also an example.
How can I make sure that external clock is locked properly in cpp.
Thanks in advance
-Burak