I’m hoping to use the USRP2 and a FLEX400 board to receive RF and a
1-bit digital stream simultaneously.
As I understand it (feel free to correct me), this can be done with the
USRP1 by loading a the gr-gpio FPGA image, which will replace the LSB of
the incoming data with the state of one GPIO pin.
Has anything similar been done for the USRP2?
Is anyone planning to add this function to an FPGA image?
Are there other ways to do it?
Any help would be greatly appreciated.
This email, including any attachments, is only for the intended
addressee. It is subject to copyright, is confidential and may be
the subject of legal or other privilege, none of which is waived or
lost by reason of this transmission.
If the receiver is not the intended addressee, please accept our
apologies, notify us by return, delete all copies and perform no
other act on the email.
Unfortunately, we cannot warrant that the email has not been
altered or corrupted during transmission.