For whoever is interested, I have a branched revision of the USRP1 FPGA
code ready that supports 16, 8, 4, 2, and 1-bit quantization. The
Verilog code is available for review in my developer’s branch of the GNU
Radio SVN repository here:
You will find all modifications in the rx_buffer.v file. This is only a
USRP modification. I’ve not added support for the new quantization
levels in the host-side GNU Radio code, and I will not be able to afford
the time to do so. If you’d rather not compile the .rbf file yourself,
I can email it to you on request.
The code I changed now supports all quantization levels across 2, 4, 6,
or 8 channels, and is optimally fast (meaning that it is not
theoretically possible to further increase the maximum sample rate for
any combination of quantization and #channels settings).
The configuration outputs data in little-endian format. For example, a
single word of 2-bit, 2-channel data looks like this:
16 14 12 10 8 6 4 2 0
| Q3 | I3 | Q2 | I2 | Q1 | I1 | Q0 | I0 |
Where I0 is sample index 0, I1 is sample index 1, etc. “I” represents
channel 0, “Q” represents channel 1.
The only remaining limitation to maximum USRP bandwidth is the minimum
settable decimation rate. If one were to remove the CIC filter and the
half-band filter, and if the rest of the FPGA code can handle it, we
could have a full 64 MHz sample rate for quantization levels low enough
that the USB connection could still handle the data rate.
Let me know if you have any questions or comments.