We are trying to setup a MIMO node using a USRP motherboard and two
xcvr2450. Theoretically the maximum allowable transmission bandwidth
using two antennas simultaneously is 4 MHz or 8 MHz if using a single
antenna (limited by the bandwidth of the USB port). However, we have
that the maximum affordable aliasing free bandwidth is approximately 2
due to the poor antialiasing performance of these filters. As we need
bandwidth, the question is: Do you think it could be possible to put a
better interpolation filter that fits into the FPGA while mantaining two
transmission and reception chains?
Related improvements are already done:
The problem is that this modification resource usage is about 96% and
one receive and transmit chains are enabled, thus, losing MIMO
For maximum bandwidth we think that fixing the total interpolation rate
32 (supressing the CIC filters) and doing a better (but resource
filtering could be a solution.
Thanks in advance