USRP MIMO node bandwidth

Dear all.

We are trying to setup a MIMO node using a USRP motherboard and two
xcvr2450. Theoretically the maximum allowable transmission bandwidth
when
using two antennas simultaneously is 4 MHz or 8 MHz if using a single
antenna (limited by the bandwidth of the USB port). However, we have
seen
that the maximum affordable aliasing free bandwidth is approximately 2
MHz
due to the poor antialiasing performance of these filters. As we need
more
bandwidth, the question is: Do you think it could be possible to put a
better interpolation filter that fits into the FPGA while mantaining two
transmission and reception chains?

Related improvements are already done:
http://gnuradio.org/redmine/issues/show/382

The problem is that this modification resource usage is about 96% and
only
one receive and transmit chains are enabled, thus, losing MIMO
capabilities.
For maximum bandwidth we think that fixing the total interpolation rate
to
32 (supressing the CIC filters) and doing a better (but resource
expensive)
filtering could be a solution.

Thanks in advance

Óscar

On Mon, Jan 18, 2010 at 11:46:53PM +0100, Óscar González Fernández wrote:

transmission and reception chains?
What is the amplitude of the signals you’re sending?
If you need more linearity, try sending smaller signals.

Eric

On Tue, Jan 19, 2010 at 11:19:04AM +0100, Óscar González Fernández wrote:

The effect we observe doesn’t seem to be a non linear effect due to high
signal amplitude. Lowering the amplitude doesn’t solve the problem. For
example, when we transmit a 1 MHz tone we can see that a spurious tone
appears at -3 MHz (referred to the carrier frequency) when using an
interpolation rate of 16 (4x at the AD9862 and 4x at the FPGA). So, that
spurious seems to be aliasing. Can you corroborate this?

Óscar

Sorry, as Matt pointed out to me off-line, I wasn’t answering the
question that you asked.

Eric

It is my fault, I have read my first question and I have realised it
isn’t
well written.

Summarizing, the question is:

Do you think it can be possible to replace the CIC interpolation filters
by
a better ones in spite of losing variable interpolation rate
capabilities?
The only requirement is keeping the two TX and RX chains (and fitting
into
the FPGA). What is the current FPGA resources usage? and the expected
after
modifications?

P.S:
For our purpose, even de DDC in the FPGA can be supressed.

Óscar

El 19 de enero de 2010 20:58, Eric B. [email protected] escribió:

The effect we observe doesn’t seem to be a non linear effect due to high
signal amplitude. Lowering the amplitude doesn’t solve the problem. For
example, when we transmit a 1 MHz tone we can see that a spurious tone
appears at -3 MHz (referred to the carrier frequency) when using an
interpolation rate of 16 (4x at the AD9862 and 4x at the FPGA). So, that
spurious seems to be aliasing. Can you corroborate this?

Óscar

El 19 de enero de 2010 03:00, Eric B. [email protected] escribió:

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