Thanks for your quick response. In regards to your comments:
Are you running one of our standard fpga images, or are you using one that
you have modified?
Yes. I am using the standard FPGA code distributed with GNU Radio
3.0.3 - the latest stable release). I did not write my own verilog code.
It’s seriously unlikely that the contents of the mux register is getting
I am also skeptical that the mux register is randomly changing. However,
am very certain that the transmitter is flipping the IQ channels. I have
verified that this is definitely happening at the transmitter. In the
antenna transmitter, setting the mux value to (0x0098) prior to sending
packet seemed to solve this problem, but not in the 2-antenna case.
some details about my USRP setup and the nature of the bug that I’m
observing might help in understanding this problem.
Below is a boiled down list of method calls which describe how I’ve set
the transmitter chain in our transceiver:
self.u = usrp.sink_c()
self.subdev1 = usrp.selected_subdev (self.u, (0,0) )
self.subdev2 = usrp.selected_subdev (self.u, (1,0) )
In our experiments we transmit packets, encoded using our MIMO physical
layer, across the USRP (after appropriate padding). I’ve observed that
some random number of consecutive packets, I receive a packet whose I-Q
channels have been flipped. It took a considerable amount of effort to
diagnose and verify that this was the problem, but I am very certain now
that this is what is happening at the transmitter. I hope that this
shed some more light on the problem and help in finding a solution.