USRP-FX2 interface / GPIF & FPGA f/ware / DDC specs

Hi again,

Finally managed to get my FX2 firmware onto my custom
board.

My intention is to mimic a reduced set of USRP
functions on my custom board to allow me to use
higher-level python modules to verify that my ADC’s
are working (a simple oscilloscope output for example)

Obviously, my FPGAs are different and will require
custom firmware.

USRP-FX2 interface - As I understand it, all control
calls to endpoint 0 are handled within the FX2 and do
not require the involvement of the FPGA - is this
correct? If not, then how do you setup the FPGA (once
configured)? e.g. enable Rx or turning on debug LEDs

GPIF / FPGA firmware - How many GPIF waveform
configurations do you implement? Also, when you
configure your Altera I understand that this is done
in a serial bit mode, is this embedded into the GPIF
setup, or do you handle FPGA configuration explicitly
using the 8051 core.

Please could you point me to the correct FX2 source to
determine your GPIF CTLx/RDYx lines and waveform
decriptions, so that I can adjust code where necessary
(my board will certainly have different pins tied
between the FX2 GPIF lines and the FPGA)

DDC specs - finally, in order to capture narrow-band
data for processing by GnuRadio, I’ll need to put a
DDC in place. Please could you tell me an
appropriate/realistic output bandwidth or complex
sample rate that will work well with USB 2 and the
Python graphical display modules.

Thanks yet again

Cheers
Kalen


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On Tue, Jul 04, 2006 at 07:53:51AM +0100, Kalen Watermeyer wrote:

Obviously, my FPGAs are different and will require
custom firmware.

USRP-FX2 interface - As I understand it, all control
calls to endpoint 0 are handled within the FX2 and do
not require the involvement of the FPGA - is this
correct? If not, then how do you setup the FPGA (once
configured)? e.g. enable Rx or turning on debug LEDs

Yes, you understand correctly.

GPIF / FPGA firmware - How many GPIF waveform
configurations do you implement?

Two: fifoRd and fifoWr

Also, when you configure your Altera I understand that this is done
in a serial bit mode, is this embedded into the GPIF setup, or do
you handle FPGA configuration explicitly using the 8051 core.

We bit bang the FPGA configuration from the 8051.

Please could you point me to the correct FX2 source to
determine your GPIF CTLx/RDYx lines and waveform
decriptions, so that I can adjust code where necessary
(my board will certainly have different pins tied
between the FX2 GPIF lines and the FPGA)

All of these questions can be resolved by spending a few minutes with
the schematics and the code. We used the Cypress GPIF designer (or
whatever it’s called). See gpif.gpf

DDC specs - finally, in order to capture narrow-band
data for processing by GnuRadio, I’ll need to put a
DDC in place. Please could you tell me an
appropriate/realistic output bandwidth or complex
sample rate that will work well with USB 2 and the
Python graphical display modules.

We run at pretty much anything between 8MS/s complex and 250kS/s.

Eric

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