USRP for physics project

I’m looking at using USRPs for data acquisition in a physics project
using an LFRX.
Rather than for more typical SDR applications. I’d be interested in
hearing from
anyone who’s done this.

At first however I was wondering if this application sounds feasible, is
it crazy to
use the USRP for non-SDR applications? Are their other better suited
devices?

I’d like to use it to replace this product:
http://sine.ni.com/nips/cds/view/p/lang/en/nid/209713
And possibly eventually integrate into our own PCB, I guess the n200 is
still mostly open hard/software?

So real rather than IQ data I guess. I’d like to samples at 100MS/s
14bit, and stream it
over the network, would this require changing the FPGA code?

I’ve pinged a few people off list, so apologies if this is a duplicate,
I’ll post here
if I receive a reply.

Regardless of whether you use the stock FPGA design or a custom one to
do raw data capture you are going to run up against the basic limits of
1GB/s
i.e 1Gb/S = 125MB/S = 62.5M 16bit samples/S

The stock image is always going to want to send an I and Q channel, and
has the option of either 25MSamples/S @ 16bit or 50MSample/S @ 8bits and
it’s going to pass the data through either 1 or 2 low pass FIR filters
to decimate to that data rate.
Even if you write a very custom FPGA design that packs 14bit data
efficiently and uses a raw UDP transport, you would be doing well to
achieve 70MSample @14bits over ethernet since real world performance
never quite matches theoretical.

Interesting project though, the USRP could definitely be a useful
generalized scientific data capture device.
-ian

On 06/23/2013 11:34 AM, Ian B. wrote:

Interesting project though, the USRP could definitely be a useful generalized
scientific data capture device.
-ian

I’ve used USRPs for radio astronomy for years, so, yeah :slight_smile:

But I think with a customized image you could send 100Msps of
real-mode-only data down the wire…


Marcus L.
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org

At 8bits sure, no problem, 14bits and we are into real-time lossless
data compressionanother somewhat hard but interesting project.

Unless the OP wants to only capture for short intervals, in which case I
guess you could capture to the 1M SRAM and read back data non-real time.

As Ian stated, 125 MBps is pretty much what you can get out of GbE.

If you need to record streams at higher rates, you will either need to
use a faster interface, or as one mentioned, use on-board memory in the
hope it is large enough for the duration of your recordings.

The following Nutaq solutions would allow you to stream an I&Q signal at
100MHz and above without bottleneck. That may be either in using PCIe
between the receiver and your PC, or by using the embedded 4 GB DDR-III.
http://nutaq.com/en/products/view/+nutaq-picodigitizer-125-series

You could use the ADAC250 acquisition card instead of the 16-channel one
presented in the above link.
http://nutaq.com/en/products/view/+nutaq-adac250

The default FPGA image will let you select your sampling rate from a
command line interface, so no need to mess with HDL.

Regardless of whether you use the stock FPGA design or a custom one to do raw
data capture you are going to run up against the basic limits of 1GB/s
i.e 1Gb/S = 125MB/S = 62.5M 16bit samples/S

The stock image is always going to want to send an I and Q channel, and has the
option of either 25MSamples/S @ 16bit or 50MSample/S @ 8bits and it’s going to
pass the data through either 1 or 2 low pass FIR filters to decimate to that data
rate.
Even if you write a very custom FPGA design that packs 14bit data efficiently
and uses a raw UDP transport, you would be doing well to achieve 70MSample
@14bits over ethernet since real world performance never quite matches
theoretical.

Thanks for your reply, I think I’ll go ahead and order one to play with.
I can live with 25MSamples/S for the moment and try and do some
compression later.
The I/Q stuff is more worrying, I guess I can always convert back to
real in software on the host?

It would be nicer not to have to so I may try looking at the Verilog and
see how easy it would be to make these changes. Alternatively if there’s
a contractor
out their who would be interested in doing this please mail me!