Hello to all,
I’m new gnuradio and the USRP and I was hoping somebody can provide me
with a quick answer/advice before I go digging through the source code
(I didn’t find an obvious answer looking through the wiki and
datasheets).
I have an application where I will need the USRP’s aux digital I/O to
control an antenna switching network at approximately 1 kHz
frequencies. How far up the software chain does support for the USRP’s
aux digital I/O go? Is there much support for them at the python
level? Or am I looking at writing additional stuff for the FPGA in
verilog?
Thanks,
Tyrel
I asked the same thing a year or so ago, didn’t get much of an answer.
AFAIK, there are no software hooks for the digital I/O pins. What we
ended up doing was editing the verilog such that the sign of the real
component sent to the BasicTX dboard came out on 1 I/O pin, and the
sign of the imag component went to another pin. One pin was data, the
other clock. We used the Quartus software to generate another .rbf
file, in other words. Just set the gain of the tx dboard to the min
and ignore its analog output. This worked fine for us.
-Steven
Steven C. wrote:
-Steven
I have an application where I will need the USRP’s aux digital I/O to
control an antenna switching network at approximately 1 kHz
frequencies. How far up the software chain does support for the USRP’s
aux digital I/O go? Is there much support for them at the python
level? Or am I looking at writing additional stuff for the FPGA in
verilog?
There are several ways to do this. All of the daughterboard IO pins can
be controlled from software, all the way up to the python application
level. However, if you want the pins to change quickly, you need to do
it in the FPGA. There is already a mechanism for antenna switching.
Look in the auto_tr code in db_flexrf.py
Matt
On Jan 28, 2008 11:54 PM, Matt E. [email protected] wrote:
Steven C. wrote:
I asked the same thing a year or so ago, didn’t get much of an answer.
AFAIK, there are no software hooks for the digital I/O pins. What we
ended up doing was editing the verilog such that the sign of the real
component sent to the BasicTX dboard came out on 1 I/O pin, and the
sign of the imag component went to another pin. One pin was data, the
other clock. We used the Quartus software to generate another .rbf
file, in other words. Just set the gain of the tx dboard to the min
and ignore its analog output. This worked fine for us.
I believe Johnathan is currently working on something called gr-gpio,
which will hopefully be released soon. It will basically be just this,
but it will also include RX. This will allow sending and receiving
digital i/o syncronously with the transmitted waveform, at the cost of
reducing dynamic range by 1 bit in the I and Q components of the
signal. There is a fixed delay involved, which you have to take into
account.
juha