Hi all
I’m a SDR beginner and i have a usrp b210. I need to implement a fft block on the fpga inside the usrp and pc gets the data in freq domain. I designed my fft using xilinx IP core and place it in b200_io module where input data (12-bit rx_data) convert to i-q signal (12-bit rx_i, rx_q) but i got runtime error.(codec loopback test failed).
please help me to solve this problem.
Thanks.