Unknown phase-relation between rx and tx

Hi,

Iam using
gr.sig_source_s (self.usb_freq (), gr.GR_CONST_WAVE, 0, 0, 0)
to generate a carrier and
usrp.source_c(nchan=2,decim_rate=self.interp) to resample it at the
same
frequency.

I get what I expect: 2 complex numbers which are pretty constant. But
with
every restart
of the program the phase changes (apparently by the same amount for both
channels). The
amplitude does not vary much from run to run.

It seems to me, that the phase relation between the interpolator in the
TX
and the decimator in
the RX changes with every restart.

Is there a way to “reset” the interpolator/decimator so that I get the
same
reading for every start
(as long as I don’t change frequencies) ?

Thank’s
Wolfgang

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Unless I misunderstand what you are doing, what you are describing is
the coherence error of the system. The long-answer made short is “no”.
You have to calibrate it out or otherwise live with it. The TX and RX
paths of the USRP are derived from separate hardware local oscillators
so there will always be an unknown phase error between them. What’s
worse is that it will vary slowly and dynamically as temperature and
voltage change during system operation.

Cheers,
-Jonathan

On Sun, Jun 22, 2008 at 2:42 AM, wolfgang buesser

Just to make sure:

I am using LF RX/TX-boards.
TX and RX are on the subdev (thus using the same AD9862)

Thanks
Wolfgang

Jonathan F.-2 wrote:

-Jonathan

same
TX


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That’s true, but their are two frequency synthesizers (ADF4360-0 on my
flex2400) on each flex daughter card (one for TX and one for RX – or
more generically one for each sub-subdevice). On the basic daughter
cards (which only have one sub-subdevice) there is only one
synthesizer, but you need a second daughter card to complete the path
(one for TX, one for RX).

Ultimately, this is not a software (firmware fix) or sampling problem
(use the same ADC or supply sync signal). This is a physics problem
that results from using two independent oscaillators that are not
phase locked to each other. Resultingly, you need a hardware fix to
achieve coherence. That said, this is a problem that will manifest
itself in your real-world application and is not easy to solve except
by phase locking the oscillators through a cable (which doesn’t work
well for anything, except really short separation distances).

What is your ultimate application?

Cheers,
-Jonathan

On Sun, Jun 22, 2008 at 3:58 AM, wolfgang buesser

Sorry,

I may be completely off track, but I dont’ see any clock-source on the
schematic of my
LF-RX/TX (not basic RX/TX).
As far as I understand they only process the signals as baseband without
any
frequency
conversion.
Yes, I have to use 2 daughter-boards (one LF-RX and one LF-TX) to
complete
the path,
but if they both transfer the signals to the same AD9862 without any
conversion I expect
the phase-correlation to be an issue of the interpolator/decimator
inside
the AD9862 or
potentially the FPGA-code.

Thank’s
Wolfgang

Jonathan F.-2 wrote:

that results from using two independent oscaillators that are not

voltage change during system operation.

gr.sig_source_s (self.usb_freq (), gr.GR_CONST_WAVE, 0, 0, 0)
channels). The
(as long as I don’t change frequencies) ?


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On Sun, Jun 22, 2008 at 05:21:41AM -0700, wolfgang buesser wrote:

Sorry,

Wolfgang
Wolfgang,

The standard configuration uses the built-in digital upconverter in
the AD9962 on the transmit path. One problem with that is that
although we have control of the frequency tuning word, there’s no way
to control or reset the absolute phase of the the NCO in the DUC.

On the downconversion side, we do have control over the absolute
phase, and thus can ensure coherence.

From usrp_standard.h:

/*!

  • \brief Set the digital down converter phase register.
  • \param channel which ddc channel [0, 3]
  • \param phase 32-bit integer phase value.
    */
    bool set_ddc_phase(int channel, int phase);

Once upon a time, we did handle the digital upconversion in the FPGA,
but it’s been years since that code was used or tested. We use the
one in the AD9862 to save resource in the FPGA. If you only need a
single tx and rx path, there’s most likely enough room in the FPGA and
you could try to resurrect that code (fpga and host).

Eric

On Sun, Jun 22, 2008 at 02:42:03AM -0700, wolfgang buesser wrote:

every restart
(as long as I don’t change frequencies) ?

Thank’s
Wolfgang

This is the AD9862 digital-up-converter issue.

IIRC it does come out of powerup in a constant state. I’m not sure
that this will be useful, but if you never set the digital
upconverter, the absolute phase will remain constant.

Eric