Okay, so we’re trying to get read/write registers to work correctly, and
we’re trying to understand how a register read/write currently works
using the following methods:
_write_fpga_reg()
_write_oe()
We are monitoring the serial I/O enable signal using a logic analyzer
and writing to registers using the top two methods. When using them, we
never see the serial I/O enable signal asserted like we think it should.
So we’re wondering, what happens when these methods are called?
Second, we are trying to re-write serial i/o to support the read/write
C/S packets but do not understand serial i/o that well. We don’t quite
understand the input and output. Can anyone explain it at all, so we
understand what we need to change about it and what our new design is
going to look like?
Thanks!
George
On Mon, Aug 13, 2007 at 02:01:05PM -0400, George N. wrote:
Okay, so we’re trying to get read/write registers to work correctly, and
we’re trying to understand how a register read/write currently works
using the following methods:
_write_fpga_reg()
_write_oe()
If you trace through the code, you’ll see that _write_oe ends up
calling _write_fpga_reg.
We are monitoring the serial I/O enable signal using a logic analyzer
and writing to registers using the top two methods. When using them, we
never see the serial I/O enable signal asserted like we think it should.
So we’re wondering, what happens when these methods are called?
I’m not sure why you’re looking at any of the serial buses at this
point. They are completely unrelated to anything having to do with
writing an FPGA register using inband signaling 
Also, after face-to-face discussion with Matt over the past few days,
it turns out that we will not need to implement either the I2C or SPI
interfaces in the FPGA for the USRP1.
Second, we are trying to re-write serial i/o to support the read/write
C/S packets but do not understand serial i/o that well. We don’t quite
understand the input and output. Can anyone explain it at all, so we
understand what we need to change about it and what our new design is
going to look like?
Summary: don’t worry about SPI or I2C i/o from the FPGA.
To control the PLL and rx gain on the RFX-* boards on the USRP1, we’ll
move some resistors on the RFX boards, enabling an alternate control
mechanism via the daughterboard i/o pins. More on that later.
Thanks!
George
Eric
On Mon, Aug 13, 2007 at 03:22:23PM -0400, Zhuocheng Y. wrote:
What about writing to normal registers? We are not interested in
writing to I2C or SPI right now. We just want to write to FPGA
registers.
Understood. The registers are defined in verilog using either
setting_reg or setting_reg_masked. I think in the inband-signaling
(IBS) case the only difference is who supplies the addr, strobe and
clock.
Eric