UHD fpga code compile error

Hi all,
I compile uhd fpga code meet a lot of errors.
I use quartus II 9.1 web edition.
I directly open the fpga project
file(EttusResearch-UHD-Mirror-81e891f\fpga\usrp1\toplevel\usrp_std\usrp_std.qpf)
then choose menu Processing->start compilation then meet a lot of
errors.
I think the errors major cause by some file can not be found like that:
Error (10054): Verilog HDL File I/O error at adc_interface.v(3): can’t
open
Verilog Design File “…/…/firmware/include/fpga_regs_common.v”

On 04/07/2011 03:28 AM, James Jordan wrote:

That quartus code hasn’t needed to be recompiled in the last 20 years. I
suspect that the relative paths were not updated when the code moved.

Can you try this diff?

diff --git a/fpga/usrp1/toplevel/usrp_std/usrp_std.v
b/fpga/usrp1/toplevel/usrp_std/usrp_std.v
index 8b29a9c…83a89cb 100644
— a/fpga/usrp1/toplevel/usrp_std/usrp_std.v
+++ b/fpga/usrp1/toplevel/usrp_std/usrp_std.v
@@ -28,8 +28,8 @@
// Uncomment the following to include optional circuitry

include "config.vh" -include “…/…/…/firmware/include/fpga_regs_common.v”
-include "../../../firmware/include/fpga_regs_standard.v" +include “…/…/…/…/firmware/fx2/common/fpga_regs_common.v”
+`include “…/…/…/…/firmware/fx2/common/fpga_regs_standard.v”

module usrp_std
(output MYSTERY_SIGNAL,

-Josh

I change the all
`include “…/…/…/firmware/include/fpga_regs_common.v”

`include “…/…/…/firmware/include/fpga_regs_standard.v”

to

include "../../../../firmware/fx2/common/fpga_regs_common.v"include “…/…/…/…/firmware/fx2/common/fpga_regs_standard.v”

then compile correct. I think this change should be added to the git
repo.

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