UHD Announcement - November 07th 2011

Hello list,

A bunch of great work has been merged into the master. For those
following the work on the master branch, and not a release, you will
need to update your firmware and FPGA images:

http://code.ettus.com/redmine/ettus/projects/uhd/wiki#Binary-downloads
http://files.ettus.com/uhd_releases/master_images/


– RX bandwidth doubled with complex-int8 mode

One may wish to send alternative formats over the wire: for example to
increase bandwidth at the expense of precision. All USRPs now support
receiving complex-int8 over the wire (previously only complex-int16
implemented). To make use of this feature, see the notes below on the
API changes.


– Stream API changes

There has been some fundamental changes to the UHD API in terms of
streaming. Before I continue, I should state that the recent changes are
backwards compatible. All code out there, C++ or python will continue
to compile and run.

Basically, rather than calling send() or recv(), on a device object, you
create a streamer object with some parameters and call send()/recv() on
that streamer.
http://files.ettus.com/uhd_docs/doxygen/html/stream_8hpp.html

Essentially, each streamer represents a group of channels with its own
sample rate and format. This will allow users to receive from multiple
heterogeneous channels, and support the complex-int8 type as mentioned
above.

The best way to understand this is to take a look at the examples
directory. All examples have been updated to reflect the API changes.


– Stream API and GNURadio

The USRP source and sink blocks have been updated to reflect the new
API; as well as the python and C++ examples and applications. The gr-uhd
component will continue to compile with the UHD releases and the recent
work on master.

The source and sink block feature new constructors which take the stream
args as a parameter. With stream args, users can specify the number of
channels and host format, and more importantly, the wire format to
support the new complex-int8 feature.

Unfortunately, the source and sink blocks do not yet support
heterogeneous channels (different rates and/or IO types). This is too
much change to me to handle at the moment. I believe the implementation
would involve multiple work functions (threads), one for each streamer.

For code examples, see any of the gr-uhd/examples or gr-uhd/apps. Or my
personal favorite: make a flow graph in GRC, and inspect the generated
code.


– Clock config API changes

I am deprecating clock config as the method of configuring the device’s
time reference and clock reference. All calls to set clock config will
continue to work, they are just mapped into the new interface.

This applies UHD, gr-uhd, C++, and python: Clock config has been split
into two separate calls: set_time_source() and set_clock_source(), where
each source has a name identified by a string, such as “external”,
“internal”, “mimo”, “gps”. Users may also query the list of possible
time or clock sources.
http://files.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html#a57a5580ba06d7d6a037c9ef64f1ea361

GRC blocks have been updated to generate calls for the API changes.


– Hooks for IQ balance and DC offset correction

Hooks have been added into UHD, gr-uhd, c++, and python to configure the
various correction registers in the FPGA. Users can use this to control
the DC offset correction and IQ imbalance correction arithmetic in the
FPGA.

http://files.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html#a7beb49c1a04a81b3e7569db482453746

On Tue, Nov 8, 2011 at 5:11 AM, Josh B. [email protected] wrote:

Hello list,

A bunch of great work has been merged into the master.


– Hooks for IQ balance and DC offset correction

Hooks have been added into UHD, gr-uhd, c++, and python to configure the
various correction registers in the FPGA. Users can use this to control
the DC offset correction and IQ imbalance correction arithmetic in the FPGA.

This means that calling set_tx_iq_balance with (1,-1) I will get an
“inverted
spectrum” ?

G.


cpp-today.blogspot.com

Dear Josh,

I am assuming that with new IQ balance and DC offset correction methods,
we can calibrate a multi-channel USRP system for their phase and LO
offsets in real-time streaming.

May you please elaborate it a little more for our convenience: if and
how it can be achieved.

Thanks for the great work,

Khalid.

Josh B. wrote in post #1030750:


– Hooks for IQ balance and DC offset correction

Hooks have been added into UHD, gr-uhd, c++, and python to configure the
various correction registers in the FPGA. Users can use this to control
the DC offset correction and IQ imbalance correction arithmetic in the
FPGA.

http://files.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html#a7beb49c1a04a81b3e7569db482453746

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