Hello list,
A bunch of great work has been merged into the master. For those
following the work on the master branch, and not a release, you will
need to update your firmware and FPGA images:
http://code.ettus.com/redmine/ettus/projects/uhd/wiki#Binary-downloads
http://files.ettus.com/uhd_releases/master_images/
– TX bandwidth doubled with complex-int8 mode
In my last announcement, RX bandwidth was doubled with complex-int8
mode. Now for this announcement, the same capability has been developed
for the transmit direction. This means 50Msps for USRP2/N-series and 16
Msps for B100.
To make use of this feature, grab the latest master branch and set the
over-the-wire format to “sc8”.
http://files.ettus.com/uhd_docs/doxygen/html/structuhd_1_1stream__args__t.html#a0ba0e946d2f83f7ac085f4f4e2ce9578
– Controlling the dynamic range in sc8 mode
The wire format has 8 bit numbers, but the DSP has 16 bit numbers.
Naturally, users will need a way to control how those 8 bits are used
effectively. Previously, the user could supply an arbitrary scalar.
Since, the scalar wasn’t very intuitive, it has been replaced with the
following instead:
peak: specifies a fractional sample level to calculate scaling with the
sc8 wire format. When using sc8 samples over the wire, the device must
scale samples (both on the host and in the device) to satisfy the
dynamic range needs. The peak value specifies a fraction of the maximum
sample level (1.0 = 100%). Set peak to max_sample_level/full_scale_level
to ensure optimum dynamic range.
Example: Suppose that you are receiving 50 Msps with sc8 mode over the
wire and fc32 host samples. Full-scale is 1.0, but you know that you
will never see a sample above 0.3 in amplitude. Set peak=0.3 to get the
most out of 8-bit of dynamic range. GRC users: this is the stream args
parameter of the USRP source/sink block.
– A path for users to customize the DSP
I want to make it easier for users to drop in custom verilog, before, or
after the DDC/DUC, or in other places in the transmit/receive chains.
It is now possible to code custom verilog modules to a specific
interface, and to modify only the top-level makefile to tie a custom
module into the DSP chain. In addition, users can put settings registers
into their own address space which can be accessed through the UHD API
(courtesy of Johnathan C.'s user register work).
The end result is that users can create custom DSP logic and settings
without diving into the gory details of the existing DSP chains or C++
source to make mods. Clearly, this cannot cover all possible FPGA
modifications, but it should be very useful for most.
A helpful read-me:
http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/README.txt
Templates for custom module interfaces:
http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/show/fpga/usrp2/custom