Tx Path


#1

Hi, I was looking at the UsrpTxModifications page in wiki, I want to
understand how the Tx goes.
my question is what is the spi_bus that goes into the data block and
come out of the command block, is it internal in the FPGA? looking at
the UsrpRfxDiagrams in the first digram I see the signal come out of the
FPGA as I and Q, But looking into the data sheet of the AD9862 there is
only one input as the Tx data and from there it become as I and Q
signals. Is there any detailed diagram of the ‘inside’ FPGA, I have
know two different diagram one on the wiki page the other is writing by
Oussama S.( I have it as pdf), which one is the write one. Another
thing I want to send two signals from two tx boards but phase shifted
from each other, is there a way to control the phase of the Tx
signal?Thank you,Anmar


#2

On 4/13/07, Anmar A. removed_email_address@domain.invalid wrote:

Hi,

I was looking at the UsrpTxModifications page in wiki, I want to understand
how the Tx goes.

my question is what is the spi_bus that goes into the data block and come
out of the command block, is it internal in the FPGA?

Currently the SPI and I2C busses are connected up to the FX2. Those
diagrams are for the mblock specification for critical timing.

You can check out what I know from the FX2 here:
http://gnuradio.org/trac/wiki/FX2

looking at the UsrpRfxDiagrams in the first digram I see the signal come
out of the FPGA as I and Q,
But looking into the data sheet of the AD9862 there is only one input as
the Tx data and from there it become as I and Q signals.

I am pretty sure the input to the AD9862 is interleaved I and Q data.

Is there any detailed diagram of the ‘inside’ FPGA, I have know two
different diagram one on the wiki page the other is writing by Oussama
Sekkat( I have it as pdf), which one is the write one.

The current USRP without mblock modifications are correct from Oussama
Sekkat. The ones that describe command and channel block FIFOs are
for mblock timing enhancements.

Another thing I want to send two signals from two tx boards but phase
shifted from each other, is there a way to control the phase of the Tx
signal?

I believe you may be able to send 2 real signals and control their
phases, but someone else here is a better authority on that than I am.

Brian


#3

Brian P. wrote:

I believe you may be able to send 2 real signals and control their
phases, but someone else here is a better authority on that than I am.

Do you know who that is?

I found a patch that Patrick has posted for phase shifting, put it
didn’t work, Did someone tried to use it, and have got it working?

Thanks
Anmar


#4

On Tue, Apr 17, 2007 at 07:25:50AM -0700, Eric B. wrote:

however at power-up it has a constant value.

Eric

Following up with “more information than you probably want”…

If you’re willing to do some work, it is possible to reprogram the
AD9862 such that the two signals sent to it are treated as two
independent real signals. This only makes sense using a
non-quadrature Tx daughterboard (e.g., Basic Tx or LF Tx). However if
you do this, you lose the use of the digital upconverter in the
AD9862.

You can work the details out by looking at the existing code in
usrp_basic.cc and usrp_standard.cc and spending a few hours with the
AD9862 data sheet :wink:

Eric


#5

On Tue, Apr 17, 2007 at 08:55:08AM +0200, Anmar wrote:

Thanks
Anmar

If you have two daughterboards you can send two independent signals.

If you start fresh from USRP power-up you can control the phase
between the transmitted signals (this also depends on the
daugherboards that you are using and how they are configured.) The
power-up requirement is because from software we have no way to
control the phase accumulator in the AD9862 digital upconverter,
however at power-up it has a constant value.

Eric


#6

Eric B. wrote:

If you have two daughterboards you can send two independent signals.
yes, I have two daughterboards(Basic TX). I can now send two independent
signals from the two daugterboards, but the two signals have the same
phase.

If you start fresh from USRP power-up you can control the phase
between the transmitted signals (this also depends on the
daugherboards that you are using and how they are configured.)

How can I control the phase on power-up?

The

power-up requirement is because from software we have no way to
control the phase accumulator in the AD9862 digital up converter,
however at power-up it has a constant value.

But if the two signals come out of the FPGA with different phase,
because each one of the signals will go to different AD9862. I would
think that the phase should be controlled from the FPGA and the AD9862
will have nothing to do with the phase, probably not :).

Anmar

Eric


#7

On Wed, Apr 18, 2007 at 01:49:36PM +0200, Anmar wrote:

daugherboards that you are using and how they are configured.)

How can I control the phase on power-up?

IIRC, they come up with the same phase.

The

power-up requirement is because from software we have no way to
control the phase accumulator in the AD9862 digital up converter,
however at power-up it has a constant value.

But if the two signals come out of the FPGA with different phase,
because each one of the signals will go to different AD9862. I would
think that the phase should be controlled from the FPGA and the AD9862
will have nothing to do with the phase, probably not :).

You can control the phase in the FPGA. However, we’re using the
digital upconverter in the AD9862. That DUC has its own phase
register.

Eric


#8

Eric B. wrote:

On Wed, Apr 18, 2007 at 01:49:36PM +0200, Anmar wrote:

You can control the phase in the FPGA. However, we’re using the
digital upconverter in the AD9862. That DUC has its own phase
register.

Loading the code below, I connected the two daughterboard’s to the X and
Y channel of the scoop. every time I load the code I get a different
angel on the scoop(but there is a constant change with it). how can I
explain why this is happening?

def main():
interp = 128
waveform_type = gr.GR_COS_WAVE
waveform_ampl = 16000
waveform_freq1 = 40e3
waveform_freq2 = 10e3
waveform_offset = 0
fg = gr.flow_graph ()
sink = usrp.sink_c (0, interp)
sink.set_nchannels(2)
sink.set_mux(0xba98)
usb_freq = sink.dac_freq() / interp
siggen1 = gr.sig_source_c (usb_freq,
gr.GR_SIN_WAVE,
waveform_freq1,
waveform_ampl,
waveform_offset)

    siggen2 = gr.sig_source_c (usb_freq,
                                   gr.GR_SIN_WAVE,
                                   waveform_freq2,
                                   waveform_ampl,
                                   waveform_offset)

inter = gr.interleave(gr.sizeof_gr_complex)
fg.connect (siggen1, (inter, 0))
fg.connect (siggen2, (inter, 1))
fg.connect (inter, sink)
fg.start()
raw_input(‘Press enter to stop\n’)
fg.stop()

if name == ‘main’:
main()

thanks
anmar

Eric


#9

Eric B. wrote:

On Fri, Apr 20, 2007 at 08:26:25PM +0200, Anmar wrote:

explain why this is happening?
OK, here goes, one more time: there is state in the AD9862 – its DUC
phase register – that we can’t control from software.

Do you understand what that means?
Yes
Have you looked at the AD9862 data sheet?
Yes, and I have red about the Tx moeds and the clock timing.

If you cycle power on the USRP each time before you run the
experiment, do you get repeatable results?
well, today I tried without each time powering on the usrp, and I get
repeatable results, but when I load different code like am_tx then there
will be a small phase shift, resetting the USRP I get the normal
results. I made some pictures :).

What daughterboards are you using?
I have two basic Tx daughterboards, so each one use different AD9862. I
have a question the 2 AD9862 they both get there clock in from the usrp
motherboard, and that is the same clock?

thanks ,

anmar


#10

Anmar wrote:

What daughterboards are you using?
I have two basic Tx daughterboards, so each one use different AD9862. I
have a question the 2 AD9862 they both get there clock in from the usrp
motherboard, and that is the same clock?

The AD9862s (which are on the motherboard) both get the same clock from
AD9513 clock distribution IC. The only difference is that the clock
signal goes through separate (but identical) filters on its way to each
AD9862.


#11

On Fri, Apr 20, 2007 at 08:26:25PM +0200, Anmar wrote:

explain why this is happening?
OK, here goes, one more time: there is state in the AD9862 – its DUC
phase register – that we can’t control from software.

Do you understand what that means?
Have you looked at the AD9862 data sheet?

If you cycle power on the USRP each time before you run the
experiment, do you get repeatable results?

What daughterboards are you using?

Have you read and understood
http://gnuradio.org/trac/wiki/USRPClockingNotes ???


#12

Roshan B. wrote:>

The AD9862s (which are on the motherboard) both get the same clock from
AD9513 clock distribution IC. The only difference is that the clock
signal goes through separate (but identical) filters on its way to each
AD9862.

ok thanks a lot guys, I know enough now for trying things.