I’m trying to use clk_divider block to down the frequency of baseband PN
code in project gr-sounder to 32kHz. The time quest analysis of the
verilog code shows the result is correct.Â After the FPGA bitstream
loaded,however, the waveform of the signal still contains some high
frequency component (noise) but much more better than PN code spread
The major problem of the frequency decreasing is the transmitting signal
from the antenna doesn’t show the result of BPSK modulation in the
waveform of the signal. Could you please give some suggestions about
what the problem?
Thanks in advanced.