My questions is regarding tx_chain.v.
I am a bit confused as to how the flow of the code would proceed. There
no “always” statement in the code.
First, two instances of cic_interp are instantiated .i.e. cic_interp_i
cic_interp_q . The signal assignments happen. The most significant
i_in and q_in are assigned to signal_in of cic_interp_i & cic_interp_q.
Do both (cic_interp_i & cic_interp_q) instantiation and assignment
the execution time 0 ?
Or for that matter, all (cic_interp_i , cic_interp_q, phase_acc_tx &
tx_cordic_0) instantiations happen at time 0 ?
I am doubtful of what I am thinking above. Because I can see that
cic_interp_i’s output signal bb_i is being assigned as input in
So, if I go by my logic, then wrong assignments would happen.
Lets assume that some logic is defined for all (cic_interp_i ,
cic_interp_q, phase_acc_tx & tx_cordic_0) modules. And suppose
module logic takes 5 clock cycles to finish its task and tx_cordic_0
logic takes 8 clock cycles to finish its task. So, will tx_cordic_0 wait
5 clock cycles for cic_interp_i to finish its task, produce bb_i and
tx_cordic_0 uses this new bb_i and then takes additional 8 clock cycles
finish its task ?
So, total completion time would be 13 clock cycles ? Am I thinking right
there is something wrong ?
P.S. Excuse me if my understanding sounds naive.