Two WBX boards synchronization

GNU Radio
1

Hi all guys,

I am about to make a receiver with two WBX daughterboards. I want to
receive simultaneusly with horizontal and vertical antenna. For this
purpose I want to use 4RX FPGA image. My question signals obtained in
this
way, from two daughterboards, alligned in time?

Many thanks,

2

You haven’t stated which USRP motherboard platform, but I assume you’re
talking about the USRP1, given the 4RX image. Yes, the samples
will be aligned in time, but the relative phase will be random every
time you re-tune or start a new session.

On 2014-12-08 06:03, Nemanja S. wrote:

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3

Yes, the platform is USRP1. What is relative phase in this case if they
are
alligned in time?

4

Shouldn’t relative phase be constant and 90 degrees for example if
transmitted wave had circular polarization?

5

On 12/09/2014 04:42 AM, Nemanja S. wrote:

Shouldn’t relative phase be constant and 90 degrees for example if
transmitted wave had circular polarization?
The samples will be time-aligned, but those samples will have been
derived from two independent analog downconversion
chains, which means that the synthesized LO will have a different
relative phase (between the two sides) every time.

6

is there any way to synchronize those two clocks sources?

7

On 12/09/2014 07:32 PM, Nemanja S. wrote:

is there any way to synchronize those two clocks sources?
Not on a USRP1.

On N200, there’s support for “timed commands”, which allows both
synthesizers to be locked to the same phase when they’re re-tuned, but
that’ll
leave you with a 0/180deg ambiguity, because the mixer used on the
WBX uses a 2XLO scheme, and the LO phase splitter can’t be forced into
a specific state on tuning.

Synthesized LOs have this inherent property. Even when two synthesizers
share a common reference, it’s unpredictable what their phase will be
when they lock to the LO. More so for so-called fractional-N
synthesizers, which are what’s used in nearly everything these days. In
the case of
the WBX and SBX, they use a synthesizer from ADI (ADF4351) that has a
fairly-rare “phase resynch” feature which allows the chip to bring the
resulting LO into a particular phase relative to the reference clock,
using a hardware synchronization signal. That signal, and the FPGA code
to
make it work, is only available in the N2xx and X3xx family. The
USRP1 FPGA codebase has been utterly-frozen for many years, and there’s
zero room to do anything fancy, without leaving stuff out.

The usual way around this is to use a calibration signal that is common
to both receivers, and use that to calibrate-out the “per run” phase
difference.

8

Thank you Marcus. When I think of my application I can combine signals
after demodulator where the prolblem of phase shift is not present.
At the end I would like to ask what is the name of such architecture
where
I receive with hor and ver antennas and combine baseband signal?