I read in the Dawei Shen tutorial 4 (The USRP board) that the multilple
channels must be the same data rate and the same applies for the TX
Looking at the top level module, usrp_std.v, more preceisely the TX side
example, it seems that both tx_chain modules share the interp_rate
suppose this is why we can’t have 2 signals with two different rates.
it possible to do so by changing the verilog code.
My goal would be to be able to control the TX chain by giving it 2
interpolation rates so that it can handle two interleaved signals with
different speeds. For example, if the usb data has two intearleved
and B where B comes at a faster rate (say twice the rate), then the data
would look like the following : ABBABBABB… once this data gets to the
buffer, I have to make sure to decouple that signal accordingly and also
make sure that the interpolation rates are different for the A and B
So my question is the following: If I am able to change the verilog code
mentionned above, can I transmit/receive two signals coming at two
Thank you ahead of time.