Transmission buffer

Hi,

I am looking at the transmission buffer (tx_buffer.v) verilog code. So
it
seems that it uses two clock signals. the txclk signal is used to read
from
the fifo_4k while the usbclk signal is used to write to the fifo_4k.
What are the clock speeds for those clock signals?
I believe I read in a previous email to the mailing list that the
master_clock runs at 64MHz. Is that correct? Also, it appears to me that
the
master clock does not come form the GPIF bus of the USB controller.
Where
does that signal come from? Is it just an on board clock?
What is the speed of the usb clk?

Thank you ahead of time for any clarification on the matter.

Oussama.

Oussama S. wrote:

controller. Where does that signal come from? Is it just an on board
clock?
What is the speed of the usb clk?

Thank you ahead of time for any clarification on the matter.
The USB clock is 48 MHz, provided by the FX2

Ok. Thanks for the quick reply.
I was also wondering about the following.
One of the input to the usrp_std module is SDI. From my understading, a
serial address and serial data is sent through that input in order to
control registers inside the FPGA. What I don’t know is the origin of
the
input. It doesn’t seem to be coming from the GPIF bus.
How is the SDI signal sent from the USB to the FPGA?

Thank you ahead of time,

Oussama.

On Thu, Oct 12, 2006 at 12:10:23AM -0700, Oussama S. wrote:

One of the input to the usrp_std module is SDI. From my understading, a
serial address and serial data is sent through that input in order to
control registers inside the FPGA. What I don’t know is the origin of the
input. It doesn’t seem to be coming from the GPIF bus.
How is the SDI signal sent from the USB to the FPGA?

The 8051 bit-bangs the SDI data, clock, and strobe lines.
They are “slow” compared to other FPGA actions.
See usrp-*/firmware/src/usrp1/spi.c

- Larry

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