Testbench problem


#1

Hi Everyone:

This is a follow up of yesterday’s start/end of burst issues. I have
created a testbench to test my code. See attachment for details(only 4
files).

when simulating the code, the datain register in the file
test_chan_fifo_reader.v is set to be the wrong value. In Ln 88 of
test_chan_fifo_reader.v, send_packet(9’d128, 2’d2, 32’h0); The flag is
set to be 2. Therefore, on Ln 114, if (i == 0) datain = {3’d0, flag,
18’d0, (4*length - 8)}; datain should be set to 0x100001f8, however,
during simulation in model sim, it is begin set to 0x00001f8.

Anyone have any ideas?

Leo


#2

On 8/2/07, Zhuocheng Y. removed_email_address@domain.invalid wrote:

Hi Everyone:

This is a follow up of yesterday’s start/end of burst issues. I have created a testbench to test my code. See attachment for details(only 4 files).

I didn’t receive an attachment - could you commit to your SVN branch?

Brian


#3

The mailing list monster probably ate it for good reason!

I committed the files to leos branch:
http://gnuradio.org/trac/browser/gnuradio/branches/developers/zhuochen/simulations/burst_test

Other than that, I know nothing about them :wink:

  • George

#4

On 8/2/07, George N. removed_email_address@domain.invalid wrote:

The mailing list monster probably ate it for good reason!

I committed the files to leos branch:
http://gnuradio.org/trac/browser/gnuradio/branches/developers/zhuochen/simulations/burst_test

Other than that, I know nothing about them :wink:

Thanks. I was able to get the proper results if outside the
concatenation I declare:
length = length*4-8 ;

I think modelsim might have been doing some sign extension of your
lower bits which then knock off your top bits if it concatenates from
right to left.

Brian