Strobe signals

Hi

I read a lot of the USRP’s Verilog lately and sort of figured out what
happens on the FPGA. master_control.v generates all the control
signals as far as I understand. I would just like to know how the
strobe signals work.

Looking at master_control.v it seems as if rx_sample_strobe is always

  1. strobe_decim is a clock signal (if decim=8, strobe_decim is going
    to be an 8MHz clock)? Is this correct? hb_strobe is going to be a
    4MHz clock then and is used to tell the rx buffer how often we have
    samples available for the USB link?

Thank you.

Sebastiaan

On Sun, Aug 10, 2008 at 7:53 PM, Sebastiaan H. [email protected]
wrote:

4MHz clock then and is used to tell the rx buffer how often we have
samples available for the USB link?

rx_sample_strobe is strobed at the rate of the ADC - 64MHz. Since
this is also the master clock rate, assigning it to be 1 makes sense.

The strobe generator is here:

http://gnuradio.org/trac/browser/gnuradio/trunk/usrp/fpga/sdr_lib/strobe_gen.v

It takes in an enable signal which performs the downcount, and when
that count is reached, a one-shot pulse comes out.

The halfband filter generates it’s own output strobe here:

http://gnuradio.org/trac/browser/gnuradio/trunk/usrp/fpga/sdr_lib/hb/halfband_decim.v

The rx_buffer just gets fed samples until there is enough data
available for the FX2 to perform a DMA transfer of 512-bytes.

I think there’s an old testbench laying around somewhere that I saw if
you wanted to still simulate and watch what the signals do.

As always, I am not an authority - Matt or Johnathan are the real
experts. I just read the code.

Hope that helps.

Brian

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