On 3/8/07, [email protected] [email protected] wrote:

Fascinating subject. I think I’d very much like to experiment with

multiple ADCs and different clockings…

It becomes a very tricky subject and is very susceptible to clocking

and phase noise.

If one puts an ADC at 0, 90, 180 and 270 degrees on the clock, one

should be getting four times the sample rate and twice the bandwidth

of just one ACD, yes? I don’t see any reason why it wouldn’t work, but

I’ve become used to surprises.

If you have a sample clock running at Fs, you effectively have Fs/2

bandwidth for real signal sampling. If you add in both rising and

falling edges of the clock (0 and pi phase shifts), you can double

your Fs to 2*Fs and double your sampled bandwidth to Fs. Now, if you*

do the peak and trough of such a thing, you end up with 4 points you

are sampling, doubling your previous sampling rate and doubling your

previous bandwidth to be 2Fs - where Fs was your original sampling

frequency.

Both are an increase of 4x.

The problem I see with the above is this: to get accurate clocking,

you need a sharp edge to take the sample. A square wave works very

nicely for this. To get the 180 degree shift clock, you simply take

the falling edge of that square wave. This is relatively simple to do

and is used in many places.

When generating the 90 and 270 degree shifts, that requires a little

bit of problem solving since you don’t really have a clear

transitioning point in the middle of those flat tops to be able to

take an integral or derivative of such a wave.

Now, if you were to take a fixed frequency sinusoidal clocking source

and run it through a capacitor, the output of this capacitor should be

at a 90 degree phase shift from the original signal. If you then sent

those two clocking sources through a squaring circuit, you could

possibly get a pretty decent set of sources out of that. NOTE: I have

never done this and the thought just popped in my head - I am sure it

is very rudimentary and quite possibly does not even work.

Either way, to fully exploit that, you would have to send those

through some inverting buffer that would give them all rising edges

where they needed to be instead of both rising and falling edges. As

you can see, with all the different stages the signals have to go

through - there is a good amount of uncertainty that comes with the

phase delays of each path which all have to be matched. Significant

engineering time would have to go into the modeling and simulation of

this along with building, debugging and late night bouts of

frustration.

As another note, there may already be some discrete chips that perform

such phase shifts with very low phase noise. Let me know if you find

anything.

I wonder if some sort of beat frequency would emerge if I ran two ADCs

at different sample rates on the same signal, and what for the beat

frequency would manifest in… Or for that matter, if one used ACDs

the respective number of bits of each would divide into an infinite

decimal representation when the peak-to-peak voltage of each is equal.

By manipulating parameters like these in real-time one might be able

to gain a lot of information from repetitive signals. Maybe even do a

“derivate scan” at whatever precision you managed to manipulate your

clock at…

You lost me here.

Noise is a problem smashing the mathematical neatness into bytes, but

I seem to remember something about ‘sample aperture’, I think it was.

I suspect it does some sort of averaging of the signal, so this window

width of the sample would provide some sort of critical frequency

too… Maximum undersampling rate, maybe?

Aperture jitter is the delay that it takes your ADC to take it’s

snapshot of the analog signal after your clock has already occurred.

This is usually pretty small, but can cause some problems with there

is a very high IF and you are under sampling.

Usually this is significantly less than your input analog bandwidth

anyway.

I’m going to start looking into these issues, but if you happen to

know the answers please point me to them.

“Understanding Digital Signal Processing” by Richard G. Lyons (ISBN:

0-13-108989-7) spends a significant amount of time discussing periodic

sampling in Chapter 2. You can probably pick up a whole heck of a lot

of information from there.

Thanks for the reply,

–

Nos

Brian