Stanford talk on accelerating computation with FPGAs, 13May09


#1

[The Maxeler website seems almost entirely devoid of any technical info.
–gnu]

          Stanford EE Computer Systems Colloquium
              4:15PM, Wednesday, May 13, 2009
     HP Auditorium, Gates Computer Science Building B01
                http://ee380.stanford.edu[1]

Topic: Accelerating computation with FPGAs
with a seismic computation example

Speaker: Michael Flynn
Maxeler Technologies (and Stanford)

About the talk:

For many high performance applications the alternative to the
multicore rack is to use an accelerator assist to each multicore
node. There are a number of instances of these accelerators:
GPGPU, Specialized processors (E.G.IBM’s Cell) and FPGAs.

At Maxeler we’ve found that the FPGA array technology wins out on
performance for most relevant applications. Given the initial
area-time-power disadvantage of the FPGA in (say) a custom
designed adder this is a surprising result. The sheer magnitude
of the available FPGA parallelism overcomes the initial
disadvantage.

Using Maxeler’s FPGA compiler toolkit, it is now feasible to
transform a software application into a data flow graph mapped to
an “unconstrained” systolic array. The array structure can be
matched to the applications structure and is not constrained to
nearest neighbor communications as the FPGA provides a
generalized interconnect.

As an example we consider modeling problems in seismic data
processing. In a typical problem we realize a 2000 node systolic
array on 2 FPGA’s, each node performing an operation each 4 ns.

About the speaker:

Michael Flynn is now Professor Emeritus of EE at Stanford. He
directed the Architecture and Arithmetic group in CSL for many
years.
He is now Senior Adviser and Board Chairman at Maxeler.

Contact information:

Michael J Flynn
removed_email_address@domain.invalid[2]

Embedded Links:
[ 1 ] http://ee380.stanford.edu
[ 2 ] mailto:removed_email_address@domain.invalid

ABOUT THE COLLOQUIUM:

See the Colloquium website, http://ee380.stanford.edu, for scheduled
speakers, FAQ, and additional information. Stanford and SCPD students
can enroll in EE380 for one unit of credit. Anyone is welcome to
attend;
talks are webcast live and archived for on-demand viewing over the web.


#2

John G. wrote:

Speaker: Michael Flynn
performance for most relevant applications. Given the initial
area-time-power disadvantage of the FPGA in (say) a custom
designed adder this is a surprising result. The sheer magnitude
of the available FPGA parallelism overcomes the initial
disadvantage.

I’ll have to check out the archived version of this after it happens.

I’m a bit of a fence-sitter on using FPGAs for SDR. At what point does
it become Hardware Defined Radio again? But I suppose
that with a good compiler, and FPGAs that can be re-programmed a large
number of times, it counts as SDR :slight_smile:

I’d love to be able to compute wide-band total-power and insanely-huge
FFTs as fast as the A/Ds will go. That isn’t going to
happen with a garden-variety compute platform in the next four years.
But a parallelized FFT inside an FPGA(s) or
a GPGPU could likely tackle this without breaking into a sweat…


Marcus L.
Principal Investigator, Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org