Hi all guys,
this time :), my question is regarding soem reference book or any other
kind of literature, where I can find about how digital receiver should
designed regarding sps. Namely, my current receiver is more or less
simulation of some analog circuitry that I understand better than DSP.
example, after demodulation I use a block that is apprximation of diode
max circuit for setting the right threshold for getting dgital signal
of “analog” demodulator output. After that my bit slicer works more or
like the one found in the UART. For this reasons, the signal needs to be
highly oversampled, for example, symbol rate is 19.2kb and I use
frequency of 500ksps. When lowering sampling frequency to 250ksps, the
performance of the receiver degrades a lot, plus probably to many
processing effort than it should be.