Something about xcvr2450 daughterboard

Dear everyone:
Recently I am studying the codes about daughterboard
xcvr2450(mainly usrp\host\lib\db_xcvr2450.c) and there are some problems
confuse me.
1. You see there are two steps in setting the frequency. First
daughter board tunes as close as the target fequency and return the
actual frequency . Second AD9862 perform the DUC procedure according to
target fequency and actual frequency . But in function
xcvr2450::set_freq() the so called actual_freq is set equal to
target_freq and the computing of actual_freq is not used(there are // at
the begining of the line). Why??
2.Accoring to the table12 in the datasheet of MAX2829, we derive the
divider ratio either using
.We should divide 20M.But it seems in
function xcvr2450::set_freq() 64M/3 is used to be divided instead of
Any of your answers will be very appreciated.Thank you.

On 12/07/2011 11:05 PM, signalswdm wrote:

2.Accoring to the table12 in the datasheet of MAX2829, we derive the
[email protected]
You should probably be looking at the UHD version of the XCVR code,
since the “classic” stuff hasn’t been touched in over two years.

The XCVR board has a reference divider on board, and it looks like it is
(in UHD), always set to divide the incoming master clock by either
2 or 3, depending on the master clock. The reference clock going into
the MAX2829 can be up to 40Mhz, according to the data sheet.