I have some questions (prepared from a while before you have been
USRP2 schematics so excuse me if some of them can be answered from your
How USRP2 boots? and how the FPGA firmware is loaded?
What is USRP2 ADC chip? Is there an auxiliary ADC?
What is USRP2 DAC chip? Is there an auxiliary DAC?
Is there auxiliary Digital I/O?
How USRP2 DDC is implemented ? How many CIC stages it contains?
How USRP2 DUC is implemented ? How many CIC stages it contains?
If DDC contains HBF, How many taps it has?
What is USRP2 minimum and maximum decimation values? is odd
What is USRP2 minimum and maximum interpolation values? is odd
10)What is USRP2 default IP address and subnet mask?
Does USRP2 respond to network ping command?
What is USRP2 reference clock stability?
With Basic TX board, USRP1 can generate maximum of 44 MHz frequency,
What USRP2 is capable of ?
What is USRP2 overrun message?
What is USRP2 underrun message?
What are the most important (hot) trunk USRP2 code that we need to
to understand USRP2 architecture, configuration and operation?
How much USRP2 FPGA resources does the currently FPGA firmware
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