Some USRP2 Questions


#1

Hi Matt,

I have some questions (prepared from a while before you have been
submitted
USRP2 schematics so excuse me if some of them can be answered from your
schematics).

  1. How USRP2 boots? and how the FPGA firmware is loaded?

  2. What is USRP2 ADC chip? Is there an auxiliary ADC?

  3. What is USRP2 DAC chip? Is there an auxiliary DAC?

  4. Is there auxiliary Digital I/O?

  5. How USRP2 DDC is implemented ? How many CIC stages it contains?

  6. How USRP2 DUC is implemented ? How many CIC stages it contains?

  7. If DDC contains HBF, How many taps it has?

  8. What is USRP2 minimum and maximum decimation values? is odd
    decimation
    possible?

  9. What is USRP2 minimum and maximum interpolation values? is odd
    interpolation possible?

10)What is USRP2 default IP address and subnet mask?

  1. Does USRP2 respond to network ping command?

  2. What is USRP2 reference clock stability?

  3. With Basic TX board, USRP1 can generate maximum of 44 MHz frequency,
    What USRP2 is capable of ?

  4. What is USRP2 overrun message?

  5. What is USRP2 underrun message?

  6. What are the most important (hot) trunk USRP2 code that we need to
    check
    to understand USRP2 architecture, configuration and operation?

  7. How much USRP2 FPGA resources does the currently FPGA firmware
    needs?

Best Regards,

Firas


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#2

Firas A. wrote:

Hi Matt,

I have some questions (prepared from a while before you have been submitted
USRP2 schematics so excuse me if some of them can be answered from your
schematics).

  1. How USRP2 boots? and how the FPGA firmware is loaded?

The CPLD (a Xilinx XC9572) reads the 1st megabyte from the SD card and
writes to the FPGA config pins in slave-serial mode. One the FPGA is
configured, it requests the firmware for the aeMB processor from the SD
card. After that the CPLD is switched over to passthru mode and the
FPGA has direct access to the SD card under program control.

  1. What is USRP2 ADC chip? Is there an auxiliary ADC?

The main ADC is the LTC2284, used at 100 MS/s. There is an auxiliary
ADC, the AD7922, for each dboard connector.

  1. What is USRP2 DAC chip? Is there an auxiliary DAC?

AD9777. The auxiliary DACs are AD5623

  1. Is there auxiliary Digital I/O?

The same 16 digital IOs, SPI, and I2C to each daughterboard connector.
The whole interface to the daughterboards is the same as the USRP1,
except instead of it being implemented all in the AD9862, it is done
with the following set:

LTC2284
AD9777
2x AD5623
2x AD7922
  1. How USRP2 DDC is implemented ? How many CIC stages it contains?

Very similar to the USRP1, with a 4 stage CIC

  1. How USRP2 DUC is implemented ? How many CIC stages it contains?

Again very similar, with a 4 stage CIC

  1. If DDC contains HBF, How many taps it has?

The DDC and DUC each contain 2 halfband filters. The high rate one has
7 taps and the low rate one has 31 taps.

  1. What is USRP2 minimum and maximum decimation values? is odd decimation
    possible?

Minimum interp and decim are 4. Maximum is 512.

If you use odd decimation or interpolation, you just get CIC with no
halfbands. If you use an even rate but not a multiple of 4, you just
get one halfband (the low rate one). If your rate is a multiple of 4,
you use both halfbands.

  1. What is USRP2 minimum and maximum interpolation values? is odd
    interpolation possible?

same as decimation

10)What is USRP2 default IP address and subnet mask?

The standard USRP2 FPGA image does not use IP, just raw ethernet.

  1. Does USRP2 respond to network ping command?

No, but we have our own, find_usrps

  1. What is USRP2 reference clock stability?

About 20 ppm unless you lock to an external reference.

  1. With Basic TX board, USRP1 can generate maximum of 44 MHz frequency,
    What USRP2 is capable of ?

U


#3
  1. With Basic TX board, USRP1 can generate maximum of 44 MHz frequency,
    What USRP2 is capable of ?

44 MHz is the highest frequency in the first nyquist zone on the USRP1.
Much higher frequencies can be used in the higher zones.

The USRP2 takes 100 MS/s rates and interpolates up to 400 MS/s. Direct
frequencies up to ~170 MHz should be usable.

  1. What is USRP2 overrun message?

Currently overruns are shown on the UART port, not on the host. They
are shown with a “O”. The reality is that you should never see them.
If the host computer can’t keep up you will see “S” messages in the
terminal on the host, standing for “sequence number error”.

  1. What is USRP2 underrun message?

Underruns are shown on the UART port as “U”.

  1. What are the most important (hot) trunk USRP2 code that we need to check
    to understand USRP2 architecture, configuration and operation?

In the FPGA code, the tx_control.v and rx_control.v show inband
signalling, dsp_core_rx and dsp_core_tx show the DSP, and u2_core.v is
the top level. In the firware, start with txrx.c.

  1. How much USRP2 FPGA resources does the currently FPGA firmware needs?

37 out of 40 block RAMs, 16 or 18 of the 40 multipliers, and about 35 to
40% of the logic area.

Matt


#4

Hi Matt,

Thank you for the answers. I will try to add them to USRP2 FAQ Wiki.

One thing is not clear which is the TX path interpolation.

In RX path:

if ADC sampling = 100MHz,
and if Min decimation = 4
=> max IF bandwidth = 25MHz
=> Max IF Ethernet rate = 4 bytes per sample * 25 MSPS = 100 Mbyte/sec =
800
Mbit/sec (Every thing is clear)

But this is not clear in TX path because:

If Max IF Ethernate rate = 100 Mbyte/sec => Max TX IF bandwidth = 25
MHz
and if min interpolation = 4 (as you said in your previous email)
=> DAC will get 100 MSPS

But USRP2 DAC is clocked at 400 MHz, so where is the other missing
interpolation by 4 in the TX chain?

Best Regards,

Firas


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#5

Firas A. wrote:

The interpolation from 100 MS/s to 400 MS/s happens inside the DAC chip
itself. The FPGA talks to the DAC at 100 MS/s just like it talks to the
ADC at 100 MS/s. Unless you are doing something fancy, you think of the
DAC as operating at 100 MS/s.

The primary reason for the x4 interpolation to 400 MS/s is to simplify
the analog reconstruction filters. It also allows for a coarse
modulation up to 150 MHz, but I don’t anticipate that being used very
often.

Matt


#6

“Matt” == Matt E. removed_email_address@domain.invalid writes:

>> 17) How much USRP2 FPGA resources does the currently FPGA 

firmware
>> needs?
>>

Matt> 37 out of 40 block RAMs, 16 or 18 of the 40 multipliers, and 

about
Matt> 35 to 40% of the logic area.

The XC3SD1800 would probably be a good choice for a rework or similar
designs.

B.t.w.: Thanks for putting the schematics online

Uwe Bonnes removed_email_address@domain.invalid

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------