Some questions related to DUC/DDC cordic, USRP tuning process

Hi Josh and others,

I have some more questions related to DUC/DDC cordic, USRP tuning
process:

  1. When an eob tag is issued, the DUC phase accumulator on transmit DSP
    chain is reset. What about the DDC phase accumulator on receive DSP
    chain? Does it reset at well? I am asking because I have seen that the
    receive DSP chain and transmit DSP chain apply independent freq
    corrections in order to tune to the desired center RX and TX
    frequencies. In other words, is there any relation/binding between the
    DUC cordic and DDC cordic? I hope two separate/independent phase
    accumulators are used for DDC and DUC cordic’s but I want to verify.

  2. What is the tuning granularity of RF front end? I can see from USRP
    FAQ on gnuradio.org that it is 4MHz for RFX boards.
    http://gnuradio.org/redmine/projects/gnuradio/wiki/UsrpFAQDBoards#How-is-RF-tuning-accomplished-in-daughterboards

Is step size dependent on the daughterboard, mother board or both? I am
asking because when I set my USRP N200 to transmit at say 892MHz, I
observe the below values:
Actual RF freq: 892857142.847963 Hz
Actual DUC DSP freq: - 857142.847963 Hz

What does an RF frequency of 892857142.847963 tell about the step size
of RF front-end (which is RFX900)?

Thanks in anticipation,
Yu.

On 11/14/2012 12:15 PM, Zing Yu wrote:

frequencies. In other words, is there any relation/binding between
the DUC cordic and DDC cordic? I hope two separate/independent phase
accumulators are used for DDC and DUC cordic’s but I want to verify.

The DDC chain follows the same basic rules, but rather, it is controlled
by issuing stream commands. So when a receive burst is ended, the CORDIC
phase will also reset back to zero.

What does an RF frequency of 892857142.847963 tell about the step
size of RF front-end (which is RFX900)?

The step size of the RF frontend depends on the synthesizer on the
daughterboard, the reference clock (from the motherboard), and frequency
requested. Its not possible to give a general rule. But the driver can
tell you what is possible.

If it helps, boards like RFX use integer N synthesizers, so the step
size is rather large, several MHz. Boards like SBX and WBX use
fractional N, the step size is on the order of kHz.

-josh

The DDC chain follows the same basic rules, but rather, it is controlled
by issuing stream commands. So when a receive burst is ended, the CORDIC
phase will also reset back to zero.

Okay. If I understand you correctly, then if I have a GRC flow-graph
which consists of both uhd usrp source and uhd usrp sink then both
receive and transmit part of the flow-graph will be streaming samples
indefinitely. That is, the uhd usrp source keeps on receiving samples
from fpga and uhd usrp source keeps on sending samples to fpga until I
kill the flow-graph. Now, if I manage to send bursts equipped with tags,
the transmit side operates in “send N samples and done” mode but the
receive side of the flow-graph should still be running in continuous
mode. That is only the DUC cordic will reset but not the DDC cordic (in
my case). Am I right?

The step size of the RF frontend depends on the synthesizer on the
daughterboard, the reference clock (from the motherboard), and frequency
requested. Its not possible to give a general rule. But the driver can
tell you what is possible.

If it helps, boards like RFX use integer N synthesizers, so the step
size is rather large, several MHz. Boards like SBX and WBX use
fractional N, the step size is on the order of kHz.

Okay. I have done the following:

set receive center RF frequency to 892MHz, actual RF frequency was
892857142.857.
set receive center RF frequency to 896MHz, actual RF frequency was
896428571.429.
I then took the difference 896428571.429 - 892857142.857 which was
3.571428572 MHz. So, it means ~3.5 MHz is the step size for my SDR
(RFX900 + USRP N200). Right? But that step size is not an integer value.
Isn’t it weird?

Thanks for the help.

On 11/14/2012 01:11 PM, Zing Yu wrote:

from fpga and uhd usrp source keeps on sending samples to fpga until
I kill the flow-graph. Now, if I manage to send bursts equipped with
tags, the transmit side operates in “send N samples and done” mode
but the receive side of the flow-graph should still be running in
continuous mode. That is only the DUC cordic will reset but not the
DDC cordic (in my case). Am I right?

Correct. The receiver chain and transmit chain are 100% independent.

Now, it is possible to have discontinuous reception. The API to issue
stream commands to the usrp source block is exposed:

http://gnuradio.org/cgit/gnuradio.git/tree/gr-uhd/include/gr_uhd_usrp_source.h#n131

set receive center RF frequency to 892MHz, actual RF frequency was
892857142.857. set receive center RF frequency to 896MHz, actual RF
frequency was 896428571.429. I then took the difference 896428571.429

  • 892857142.857 which was 3.571428572 MHz. So, it means ~3.5 MHz is
    the step size for my SDR (RFX900 + USRP N200). Right? But that step
    size is not an integer value. Isn’t it weird?

I dont think so. For the curious, if you turn on the logging you can see
what values the tune code is calculating.

http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/host/lib/usrp/dboard/db_rfx.cpp#L399

-josh

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