Simulation of TX_path

Hello all
In order to simulate the Tx path in the FPGA we need to get a few things
clarified.

How is the interpolation rate chosen with a known Sample rate and
Transmission frequency.
I am using an N210 and i know how the Interpolations rates are used in
"
%root/host/lib/usrp/cores/tx_dsp_core_200.cpp"
Where the filters are enabled, but where does it get the interpolation
value from, and what about the interpolation value of the DAC, this is
set
to 1 or 4 depending on (freq/tickrate) .

When i select a sample rate and carrier frequency in GNU radio, what is
the corresponding tick rate, Interpolation rate and DAC settings.
What are the formulas for this, or where precisely can i get this
information?

Futhermore i want to know if the tickrate mentioned in the code is the
CLK
signal for the FPGA running at 100MHz. This is not clear to me because
this is somehow connected to “master clock rate”. And this is only
documented as avalible if Hardware changes have been made, see
“root/host/include/uhd/usrp/multi_usrp.hpp”

We are getting lost in the massive amount of undocumented and
uncommented
Verilog and C++ code.

Best
Paul M. B.

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