Simulating FPGA Testbenches

I’ve made a few small changes to the inband FPGA code to allow for
interleaving of channels, which is necessary for our application.
I’ve gotten it to compile and have done some live testing on the USRP,
and it seems to be working. I have, however, had an extremely
frustrating time trying to simulate it. I have Modelsim-Altera set up
as my EDA Simulation Tool, and the gnuradio trunk’s tb_timestamps.v as
the initial testbench.

Depending on the simulation I run, I get the following errors:
->Gate-level simulation: megacell dcfifo not found

-> RTL simulation: include config.vh not found in tx_chain.v.
Basically, the include path from Quartus is lost. Do I need a
specific modelsim project file for running this?

I’ve also read several Quartus documentation pdfs and have been unable
to find the fix. If you need more detail about the errors I’m
getting, I can supply that information when I get back to the lab.

I sincerely apologize if this is a ridiculous question… Our group
is pretty deficient in FPGA programming.

Thanks in advance,
Steve

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