Thanks for your response. I have
following queries on the sampling rates in USRP2.
1.Â Â Â Â Â Â
I set the
interpolation rate to 6. Does that mean baseband signal is fed to DAC at
rate of 100MHz/6Â = 16.6666666666 Msps?
2.Â Â Â Â Â Â
I want actually
feed 15.36 Msps to DAC which is not possible as the interpolation factor
becomes non-integer. So do you suggest me to use â€˜resamplerâ€™ to convert
16.666666 Msps to 15.36Msps?
Â I appreciate your feedback.
— On Thu, 8/4/10, Johnathan C. [email protected]
From: Johnathan C. [email protected]
Subject: Re: [Discuss-gnuradio] sampling rate of tx_sampless.cc and
To: “Krishna S” [email protected]
Cc: “Per Z.” [email protected], “gnu”
Date: Thursday, 8 April, 2010, 3:30 PM
As i am dealing with RF communication i need to know exactly what sampling rate
the USRP2 is sampling the data and sending over the air ?
This has been detailed before on this list, so you can find a more
complete explanation by searching the archives.
On the transmit side, there are two sample rate conversions
occurring in the USRP2.
The DAC operates internally at 400 Msps, but is configured to
interpolate samples presented by the FPGA by a factor of four, so the
FPGA must present samples at 100 Msps to the DAC interface bus.Â This
is the “DAC rate” parameter referred to above.
Since it is not possible to provide the USRP2 itself with 100 Msps of
data over the GbE communications interface (this would be 3.2 Gbps
plus overhead), the USRP2 FPGA implements a configurable interpolation
rate digital upconverter, allowing an interpolation rate between 4 and
In the case it is configured to interpolate by 4, then the USRP2 will
consume samples from the GbE port at 25 Msps, or 800 Gbps + overhead.
Since the signal sample format is complex baseband (I and Q in
quadrature), the Nyquist criteria allows up to 25 MHz of signal
bandwidth to be represented using 25 Msps (not 12.5 MHz, which would
be the case for a “real” signal.)
As the interpolation rate in the FPGA is decreased, the USRP2 consumes
samples from the GbE at lower and lower rates, and the amount of RF
signal bandwidth that can be represented in the sample stream goes
down accordingly.Â In the limit, at an interpolation rate of 512, one
would generate a sample stream representing ~183 KHz (100 MHz/512) for
further host processing.
The receive side is similar, but in the other direction, and there is
only one sample rate conversion.Â The ADC sample rate is 100 Msps, and
the configurable digitial downconverter in the USRP2 FPGA filters and
decimates the digitized sample stream by a factor between 4 and 512.
Thus, at the input to the FPGA, the digitized sample stream is 100 MHz
wide, but the DDC reduces and resamples this to between 25 MHz
(decimation 4) and ~183 KHz (decimation 512).
This is a long way of saying that you should use the same decimation
and interpolation rate on the transmitter and receiver to achieve the
same sample rate/bandwidth to and from the host PCs.
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