# Sampling rate of tx_sampless.cc and rx_streaming_sampless.cc

Hi,
Â Â Â i am trying to calculate at what sampling rate does the
tx_sampless.cc and rx_streaming samples.ccÂ are sending the data (file).
from 1 USRP2 to another USRP2.

i am setting interpolation as 16 at transmitter side (tx_samples.cc) and
decimation rate of 16 at receiver side (rx_streaming_samples.cc)

according to formula what i have learnt from WEB is

Tx Side :Â Sampling Rate =Â DAC rate/ Interpolation rate;

Rx Side : Sampling Rate =Â ADC rate/ Decimation rate;

are the above equation are correct for determining the sampling rate
???

Thank You
Regards
KRISHNA S

``````  The INTERNET now has a personality. YOURS! See your Yahoo!
``````

Homepage. http://in.yahoo.com/

Krishna S wrote:

Yes, it is the sample-rate on the host-side. DAC rate and ADC rate is
100MHz.

BR/
Per

Hi,
Â Â Â Â So,Â if i am setting interpolation rate 16 at transmitter
side(tx_samples.cc), according to the equation the program is sampling
at

Â Â Sampling rate = 400/16 = 25M samples/sec.

but, I am able to receive the data only at the same decimation rate
16(rx_streaming_samples.cc) , for which the program is sampling at

Sampling rate =100/16 =6.25M samples/secÂ
Â
But for me to transmit and receive data i have to send and receive at
25M samples /sec right ??

if i try to do that i.e., at receiver side samp rate = 100/4 = 25M
samples /sec

I don’t receive at all …?

everything boils down to one question ?

the sampling rate what we are talking here is the sampling rate at which
the samples have been sampled before sending to RF as discussed in
COMMUNICATION THEORY (following the Nyquist Criteria)

or the sampling rate calculated to find the allowed no.of samples/sec
the ETHERNETÂ can takeÂ to connect the host to USRP2.Â but inside the
sampling rate is different ?

As i am dealing with RF communication i need to know exactly what
sampling rate the USRP2 is sampling the data and sending over the air ?

Thanks
KRISHNA S

— On Wed, 7/4/10, Per Z. [email protected] wrote:

From: Per Z. [email protected]
Subject: Re: [Discuss-gnuradio] sampling rate of tx_sampless.cc and
rx_streaming_sampless.cc
To: “Krishna S” [email protected]
Cc: “gnu” [email protected]
Date: Wednesday, 7 April, 2010, 7:52 AM

Krishna S wrote:

[email protected]
Â Â Â

Yes, it is the sample-rate on the host-side. DAC rate and ADC rate is
100MHz.

BR/
Per

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Krishna,

My understanding is that we can regard the sample rate of the DAC and
ADC as 100MHz (although the DAC uses internally a larger rate, this is
what I have read). Thus the rate at which samples are leaving or
entering the RF sections at are 100MHz. The maximum rate at the host
side is 25MHz, then that rate is interpolated/decimated in the FPGA
to/from the 100MHz. The tx_sampless.cc and rx_streaming_sampless.cc
reads and writes from file and therefore 25MHz host sample-rate may not
be possible.

Thus you should typically use the same interpolation/decimation factor

BR/
Per

On Thu, Apr 8, 2010 at 08:30, Johnathan C.
[email protected] wrote:

In the case it is configured to interpolate by 4, then the USRP2 will
consume samples from the GbE port at 25 Msps, or 800 Gbps + overhead.

Um, that would be 800 Mbps + overhead. But one could wish

Johnathan

As i am dealing with RF communication i need to know exactly what sampling rate
the USRP2 is sampling the data and sending over the air ?

This has been detailed before on this list, so you can find a more
complete explanation by searching the archives.

On the transmit side, there are two sample rate conversions
occurring in the USRP2.

The DAC operates internally at 400 Msps, but is configured to
interpolate samples presented by the FPGA by a factor of four, so the
FPGA must present samples at 100 Msps to the DAC interface bus. This
is the “DAC rate” parameter referred to above.

Since it is not possible to provide the USRP2 itself with 100 Msps of
data over the GbE communications interface (this would be 3.2 Gbps
plus overhead), the USRP2 FPGA implements a configurable interpolation
rate digital upconverter, allowing an interpolation rate between 4 and
512.

In the case it is configured to interpolate by 4, then the USRP2 will
consume samples from the GbE port at 25 Msps, or 800 Gbps + overhead.

Since the signal sample format is complex baseband (I and Q in
quadrature), the Nyquist criteria allows up to 25 MHz of signal
bandwidth to be represented using 25 Msps (not 12.5 MHz, which would
be the case for a “real” signal.)

As the interpolation rate in the FPGA is decreased, the USRP2 consumes
samples from the GbE at lower and lower rates, and the amount of RF
signal bandwidth that can be represented in the sample stream goes
down accordingly. In the limit, at an interpolation rate of 512, one
would generate a sample stream representing ~183 KHz (100 MHz/512) for
further host processing.

The receive side is similar, but in the other direction, and there is
only one sample rate conversion. The ADC sample rate is 100 Msps, and
the configurable digitial downconverter in the USRP2 FPGA filters and
decimates the digitized sample stream by a factor between 4 and 512.
Thus, at the input to the FPGA, the digitized sample stream is 100 MHz
wide, but the DDC reduces and resamples this to between 25 MHz
(decimation 4) and ~183 KHz (decimation 512).

This is a long way of saying that you should use the same decimation
and interpolation rate on the transmitter and receiver to achieve the
same sample rate/bandwidth to and from the host PCs.

Johnathan

Hi

Thanks for your response. I have
following queries on the sampling rates in USRP2.

1.Â Â Â Â Â Â
I set the
interpolation rate to 6. Does that mean baseband signal is fed to DAC at
the
rate of 100MHz/6Â = 16.6666666666 Msps?

2.Â Â Â Â Â Â
I want actually
feed 15.36 Msps to DAC which is not possible as the interpolation factor
becomes non-integer. So do you suggest me to use â€˜resamplerâ€™ to convert
16.666666 Msps to 15.36Msps?

Krishna S

— On Thu, 8/4/10, Johnathan C. [email protected]
wrote:

From: Johnathan C. [email protected]
Subject: Re: [Discuss-gnuradio] sampling rate of tx_sampless.cc and
rx_streaming_sampless.cc
To: “Krishna S” [email protected]
Cc: “Per Z.” [email protected], “gnu”
[email protected]
Date: Thursday, 8 April, 2010, 3:30 PM

As i am dealing with RF communication i need to know exactly what sampling rate
the USRP2 is sampling the data and sending over the air ?

This has been detailed before on this list, so you can find a more
complete explanation by searching the archives.

On the transmit side, there are two sample rate conversions
occurring in the USRP2.

The DAC operates internally at 400 Msps, but is configured to
interpolate samples presented by the FPGA by a factor of four, so the
FPGA must present samples at 100 Msps to the DAC interface bus.Â This
is the “DAC rate” parameter referred to above.

Since it is not possible to provide the USRP2 itself with 100 Msps of
data over the GbE communications interface (this would be 3.2 Gbps
plus overhead), the USRP2 FPGA implements a configurable interpolation
rate digital upconverter, allowing an interpolation rate between 4 and
512.

In the case it is configured to interpolate by 4, then the USRP2 will
consume samples from the GbE port at 25 Msps, or 800 Gbps + overhead.

Since the signal sample format is complex baseband (I and Q in
quadrature), the Nyquist criteria allows up to 25 MHz of signal
bandwidth to be represented using 25 Msps (not 12.5 MHz, which would
be the case for a “real” signal.)

As the interpolation rate in the FPGA is decreased, the USRP2 consumes
samples from the GbE at lower and lower rates, and the amount of RF
signal bandwidth that can be represented in the sample stream goes
down accordingly.Â In the limit, at an interpolation rate of 512, one
would generate a sample stream representing ~183 KHz (100 MHz/512) for
further host processing.

The receive side is similar, but in the other direction, and there is
only one sample rate conversion.Â The ADC sample rate is 100 Msps, and
the configurable digitial downconverter in the USRP2 FPGA filters and
decimates the digitized sample stream by a factor between 4 and 512.
Thus, at the input to the FPGA, the digitized sample stream is 100 MHz
wide, but the DDC reduces and resamples this to between 25 MHz
(decimation 4) and ~183 KHz (decimation 512).

This is a long way of saying that you should use the same decimation
and interpolation rate on the transmitter and receiver to achieve the
same sample rate/bandwidth to and from the host PCs.

Johnathan

Send free SMS to your Friends on Mobile from your Yahoo! Messenger.

On Fri, Apr 9, 2010 at 08:58, Johnathan C.
[email protected] wrote:

If what you really mean is that you have a host PC generated sample
stream at 15.36 Msps and need to transmit it with the USRP2, then yes,
you’d set the USRP2 FPGA interpolation to 6, then fractionally
resample from 15.36 Msps to 16 Msps on the host.

Correction: resample from 15.36 Msps to 16.6666 Msps on the host.

Johnathan

On Fri, Apr 9, 2010 at 01:25, Krishna S [email protected] wrote:

1. ``````  I set the interpolation rate to 6. Does that mean baseband signal is fed to DAC at the rate of 100MHz/6  = 16.6666666666 Msps?
``````

Not quite. It means that the FPGA is interpolating and creating 6
samples on the DAC bus for every sample that is sent to it over the
GbE. Since the DAC is “consuming” samples at 100 Msps, the FPGA is
consuming samples at 100 Msps/6 from the GbE. Thus, you need to
generate (and being able to sustain) a sample stream on the host at
100 Msps/6, and by the Nyquist limit, it can contain up to ~16.666 MHz
of spectral content.

1. ``````  I want actually feed 15.36 Msps to DAC which is not possible as the interpolation factor becomes non-integer. So do you suggest me to use ‘resampler’ to convert 16.666666 Msps to 15.36Msps?
``````

The DAC always runs at 100 Msps. You need to understand this to know
what needs to happen upstream.

If what you really mean is that you have a host PC generated sample
stream at 15.36 Msps and need to transmit it with the USRP2, then yes,
you’d set the USRP2 FPGA interpolation to 6, then fractionally
resample from 15.36 Msps to 16 Msps on the host.

Depending on what the last DSP processing stage in your application
is, you may be able to “fold” this resampling into the prior stage.
For example, if the last step in your signal processing chain is a
spectral shaping filter, like a root-raised-cosine filter, then you
can reimplement this using a polyphase resampler and use the output
filter taps there. This would combine the filter and resampling
operation in one block and eliminate the need for a very high CPU
resampling block.

Where does the figure of 15.36 Msps come from?

Johnathan

> filter taps there. This would combine the filter and resampling > operation in one block and eliminate the need for a very high CPU > resampling block. > > Where does the figure of 15.36 Msps come from?

Just a guess, but that sounds like 4x the UMTS chip rate (which is
3.84 Mchips/sec). If this is the case, there is an RRC filter at the
last DSP stage typically, so your suggestion for folding this
re-sampling in is spot-on.

Regards,
John O.
CEO/System Architect
Epiq Solutions
www.epiq-solutions.com

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