Hi,
In the USRP documents it says that the ADC has a highest sampling rate
at
64Msps. From some response from the mailing group I got to know that the
sample rate is at 32Msps. Which one is the ‘REAL’ samplng rate?
If I have a signal that has a chips rate 11Mbps, assume that the
sampling
rate is 64Msps,that mean for every bit there will be 64 samples. It
sounds
impossible that the USB interface can transfer that amount of data to
the
PC, and the buffer on the board can not be enough. How shall I encounter
this problem?
BTW: I would really like to read some documents on how to reprogram
the
FPGA using Altera Quartus II, if there is any, thanks.
/Lin Ji