The new rx_buffer_inband.v is very nearly complete.
The FX2/USB interface code refers to a “FX2 Bug Fix” or “257 Bug Fix” in
the
non inband rx_buffer. I’m assuming that this bug is that the FX2 keeps
the
RD line set for 257 usbclk cycles instead of 256. The coded fix is a
256
step counter preventing the 257th read, which is cleared by the
bus_reset
signal.
But bus_reset is connected to the master_control module, which only sets
it
on a full reset. So it would seem that the FX2 is only doing the extra
RD
on the first packet transferred (after reset), not every packet. Is
that
correct?
Does anyone have any simulation waveforms (Quartus) for the FX2
interface?
Any other gotchas I should be aware of regarding the FX2 interface?
On Thu, Sep 04, 2008 at 12:21:04PM -0600, Eric S. wrote:
The new rx_buffer_inband.v is very nearly complete.
The FX2/USB interface code refers to a “FX2 Bug Fix” or “257 Bug Fix” in the
non inband rx_buffer. I’m assuming that this bug is that the FX2 keeps the
RD line set for 257 usbclk cycles instead of 256. The coded fix is a 256
step counter preventing the 257th read, which is cleared by the bus_reset
signal.
Or by ~RD (line 82)
But bus_reset is connected to the master_control module, which only sets it
on a full reset. So it would seem that the FX2 is only doing the extra RD
on the first packet transferred (after reset), not every packet. Is that
correct?
Arg. Ok, so the RD counter is cleared along with a drop of RD too. So
I
guess I can assume that RD must be cleared for at least one cycle
between
packets? Maybe some fresh air would be a good idea too.
–ets
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