Running a Test Simulation of FPGA Code with Quartus

Hello,

I’ve written a small Verilog module for the FPGA on the USRP to do phase
recovery. I’d like to test it in isolation before I try it out on the
board,
but I’m having major problems feeding Quartus two 16 bit sine and cosine
signals with a random phase offset. The idea is that q_out after the
phase
locked loop should be zero for this case, and noise for a real signal.
It
seems that the only tools for generating signals within Quartus
basically let
you manually specify integer levels for bit vectors and a bunch of other
things
for single bit wires. The alternative to using their powerless signal
generation system is to import some waveform files, the formats of which
can be
vwf/cvwf, vec, tbl, scf, and vcd. Vcd and vwf/cvwf are Quartus specific
and the
others are mostly compatibility layers with Max+Plus and such. Does
anyone know
of a tool that can generate sine waves and export waveforms in these
formats?
Or do people just burn their Verilog code to the board to test it?

Thanks,
Reid

Reid N Kleckner wrote:

Or do people just burn their Verilog code to the board to test it?

For pre-synthesis, RTL simulation and testing, I use Icarus Verilog
under Linux.


Johnathan C.
Corgan Enterprises LLC
http://corganenterprises.com

Reid-

others are mostly compatibility layers with Max+Plus and such. Does anyone know
of a tool that can generate sine waves and export waveforms in these formats?
Or do people just burn their Verilog code to the board to test it?

I’m not sure of the lookup table (LUT) capability of the Cyclone I, or
how much LUT
capacity remains in the standard USRP build…but my suggestion would be
to use LUTs
for cosine and sine data. You could make one table, and use an offset
to determine
sine vs. cosine and also adjust phase.

One advantage to this approach is that your simulation method would be
the same as in
actual logic. Plus you don’t have to mess around with importing .wav or
other data
files into the simulator, which I’ve never found straightforward and
reliable.

-Jeff

On 8/7/07, Reid N Kleckner [email protected] wrote:

Hello,

I’ve written a small Verilog module for the FPGA on the USRP to do phase
recovery. I’d like to test it in isolation before I try it out on the board,
but I’m having major problems feeding Quartus two 16 bit sine and cosine
signals with a random phase offset. The idea is that q_out after the phase
locked loop should be zero for this case, and noise for a real signal. It
seems that the only tools for generating signals within Quartus basically let
you manually specify integer levels for bit vectors and a bunch of other things
for single bit wires.

Verilog has a real type that is not synthesizable, but useful for
testbenches. I have written a copy of the ieee.math_real package from
VHDL for VHDL. It is not very fast, but it works pretty nicely.

It’s available in zhuochen’s developer directory here:
http://gnuradio.org/trac/browser/gnuradio/branches/developers/zhuochen/simulations/burst_test/math_real.v

I used it in the testbench here to create some sines and cosines:
http://gnuradio.org/trac/browser/gnuradio/branches/developers/zhuochen/simulations/burst_test/test_chan_fifo_reader.v

Let me know if you find it useful or have problems with it. Also note
that if you plan on using it with Icarus Verilog that you need one of
the latest developer snapshots as the code I wrote found some problems
in their real value handling.

It is definitely NOT recommended you just put it into an FPGA and run
with it as you really have no idea what’s going on inside there.
Accurate modeling can really help with your debugging time.

Brian