Hi, All,
In the given verilog code at

I can see RSSI is defined by 16 bits.

*value = ((v_hi << 2) | ((v_lo >> 6) & 0x3)) << 2; // format as 12-bit
the value is only assigned by 12 bits. I though the value is RSSI. But
then
it contradicts with format given in the verilog code. Or value is not

Any help is appreciated.
Fengyuan

On 03/25/2011 10:52 PM, Fengyuan Gong wrote:

then it contradicts with format given in the verilog code. Or value is

Any help is appreciated.
Fengyuan

[email protected]
I believe that the aux adcs are only 12-bit resolution.

Furthermore, only one or two daughtercards actually provide an analog

A better RSSI estimate can be produced in software:

``  source--->complex-to-mag-squared----->single-pole-iir-filter``

On 03/25/2011 07:52 PM, Fengyuan Gong wrote:

You are looking at 2 different calculations of RSSI. The first one
happens in the FPGA and uses ADC values. This is in the USRP1.

The second one happens on the host and it uses the analog signal
strength measurement on the RFX900/1200/1800/2200/2400.

Matt

RFX900/1200/1800/2200/2400 and then calculate out the analog signal
strength?

On 30/03/2011 8:33 AM, Fengyuan Gong wrote:

RFX900/1200/1800/2200/2400 and then calculate out the analog signal
strength?

That function just does a read of the AUX_ADC (apparently a 10-bit
aux_adc on USRP1), it has no notion that it’s an RSSI value–it’s
concerned.

The “calculate out the analog-signal strength” part is essentially up to
whatever upper-layer software is using the resulting aux_adc
value, and interpreting it as an RSSI.

In the case of the RFX-series boards, the aux_adc input is connected to
the analog RSSI estimator that’s built into the demodulator
chip–in this case, the sum of two (I and Q) square-law detectors,
maybe with a little bit of gain. So the aux_adc values read are
directly proportional received signal strength. It’s up to your
software to scale appropriately.

On 30/03/2011 8:33 AM, Fengyuan Gong wrote:

RFX900/1200/1800/2200/2400 and then calculate out the analog signal
strength?
You should also be aware that the analog RSSI input is the signal power
over the analog-detector bandwidth in the demodulator chip, which
is typically much wider than the bandwidth that you ultimately
process, so if you’re processing the I and Q signals for other reasons,
you
might as well also compute RSSI from those signals, which is cheap.

Also, analog square-law detectors (as used in the demod chip) typically
only produce reliable results over a narrow range of input powers,
whereas the reliability of the computed value is much better (it’s
limited in the main by the linearity of the signal-path ADCs).

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