RSSI algorithm on FPGA (rssi.v)

Hi,
you have implemented RSSI algorithm
http://ettus-apps.sourcerepo.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/sdr_lib/rssi.v
for GNUradio. I’m not very good with Verilog, but what I can tell it’s
averaging adc value that gets feed into it.

I’m asking what should I feed into this, both I and Q values or just I
or Q values from DAC? And how I should interpret results those it will
give to me? rssi is an average from I or Q values but what is over_count
value? Is there any detailed description that what equation rssi.v is
actually using?

Thank you in advance.

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