Hi,
Needed to confirm a few things:
-
Is the global clock frequency for USRP 64Mhz ?
-
Do we use this global clock frequency for FPGA on the USRP and not
the
FPGA’s clock ? Because, I think the EP1C12Q240C8 FPGA runs at much
higher
clock speeds. So, we are using
global clock to achieve synchronisation.
-
Also, is the automatic route and place tools provided by the Quartus
software, being used for FPGA ? While compiling, I see that automatic
place
and routing is happening. But still wanted to confirm if that is true or
is
it being manually configured (for already compiled rbfs) to achieve
higher
efficiency.
Please correct me if I am wrong.
Jetli.
On Dec 4, 2007 8:30 PM, Ronald J. [email protected] wrote:
Hi,
Needed to confirm a few things:
- Is the global clock frequency for USRP 64Mhz ?
Yes. It’s a fully synchronous design with FIFO boundaries where it
talks to the FX2 chip which runs at a different clock speed I believe.
- Do we use this global clock frequency for FPGA on the USRP and not the
FPGA’s clock ? Because, I think the EP1C12Q240C8 FPGA runs at much higher
clock speeds. So, we are using
global clock to achieve synchronisation.
When the FPGA is routed, there isn’t much more slack above the 64MHz
for Fmax (or so I thought). I am not sure what you mean when you
state the part runs much higher clock speeds.
What do you mean by synchronization? It is a little vague and
ambiguous.
- Also, is the automatic route and place tools provided by the Quartus
software, being used for FPGA ? While compiling, I see that automatic place
and routing is happening. But still wanted to confirm if that is true or is
it being manually configured (for already compiled rbfs) to achieve higher
efficiency.
Quartus does all the work when translating the RTL into a programming
file.
Brian