i hve 2 questions
There some registers 32 of the which are common registers 64 to 79 are
for
custom use.
what I understood all of them are written that is set from the host.
none
of them is read from host. Is there any way by which I could communicate
some message to host from FPGA.
If it is, then will the host need to pull the message…i mean keep
polling
or is it pushed from the USB controller may be by raising an interrupt.
also,
I wish to implement 2 buffers for one tx path on the FPGA. this could be
done by putting multiplexer and demultiplexer across the buffers and
select
the needed one by setting the line select lines.
Am thinking of doing this by configuring the user defined registers to
do
the line selects.
my qestion is can we access those registers from time to time and set
and
reset them as and when needed? or is it just at the start only so that
once
they are set thats the final?
am attaching a rough sketch of intended design.
On Thu, Mar 23, 2006 at 11:17:14PM -0500, amit malani wrote:
i hve 2 questions
There some registers 32 of the which are common registers 64 to 79 are for
custom use.
what I understood all of them are written that is set from the host. none
of them is read from host. Is there any way by which I could communicate
some message to host from FPGA.
There are a few registers that are read back from the host.
They’re the ones’s with names that start with FR_RB_*
They’re effectively in a different address space from the writable regs.
If it is, then will the host need to pull the message…i mean keep polling
or is it pushed from the USB controller may be by raising an interrupt.
I’m not sure if you know this, but reading or writing the FPGA
registers is a pretty slow operation. Each one is a round trip across
the USB, and we bit-bang the register address and values from the FX2
to the FPGA. [It worked for our purposes, but we weren’t trying to do
real time control with them.]
also,
I wish to implement 2 buffers for one tx path on the FPGA. this could be
done by putting multiplexer and demultiplexer across the buffers and select
the needed one by setting the line select lines.
Am thinking of doing this by configuring the user defined registers to do
the line selects.
OK.
my qestion is can we access those registers from time to time and set and
reset them as and when needed? or is it just at the start only so that once
they are set thats the final?
am attaching a rough sketch of intended design.
You can set them whenever you like, as long as it makes sense to your
code in the FPGA.
Eric