First of all, thanks a lot Eric for last piece of advice, it helped a
lot.
But it still did not clarify me completely. I am a complete novice to
the USRP, having got it a few days back. Ok, continuing with my last
topic, can you please tell me how do I program the fpga specifically as
a counter? I mean, I just wanted to know the steps involved in the
process, like generating the .rbf files. I am currently working on
Quartus II Web Edition v6.1.
Upon doing this, how can I read the data being generated by the fpga
and display it in the time domain. Also, how do I do the pin assignment
for the fpga?
Clarification of these basic doubts would do a world of good to my
project.
Thanks a lot.
Regards,
Kuntal M.
On 3/2/07, Kuntal M. [email protected] wrote:
First of all, thanks a lot Eric for last piece of advice, it helped a lot.
But it still did not clarify me completely. I am a complete novice to the
USRP, having got it a few days back. Ok, continuing with my last topic, can
you please tell me how do I program the fpga specifically as a counter? I
mean, I just wanted to know the steps involved in the process, like
generating the .rbf files. I am currently working on Quartus II Web Edition
v6.1.
Can you give a hint as to what exactly you are trying to accomplish
with your USRP setup? Unless you are already skilled with Verilog and
FPGA’s, it would seem like you have a serious potential to break your
USRP.
The majority of your questions are related to how to run Quartus II
and the Altera website does a pretty good job documenting how that is
done.
Upon doing this, how can I read the data being generated by the fpga and
display it in the time domain. Also, how do I do the pin assignment for the
fpga?
Clarification of these basic doubts would do a world of good to my project.
To look at the data being generated by the FPGA, all you must do is
look at the interface connecting the FPGA to the AD9862 to a logic
analyzer, import it into your favorite graphing software, and there is
your time domain representation of your interpolated data before it
goes through the AD9862. I wouldn’t recommend doing something along
those lines.
In fact, if you want to just see what would happen - I recommend you
start out with a simulation. I believe you an download ModelSim from
the Altera website for free and simulate the entire FPGA. I believe
Matt wrote a testbench for the top level that you can figure out.
Thanks a lot.
Regards,
Kuntal M.
Brian
On Fri, Mar 02, 2007 at 07:16:49AM -0800, Kuntal M. wrote:
First of all, thanks a lot Eric for last piece of advice, it helped a lot.
But it still did not clarify me completely. I am a complete novice
to the USRP, having got it a few days back. Ok, continuing with my
last topic, can you please tell me how do I program the fpga
specifically as a counter? I mean, I just wanted to know the steps
involved in the process, like generating the .rbf files. I am
currently working on Quartus II Web Edition v6.1. Upon doing this,
how can I read the data being generated by the fpga and display it
in the time domain. Also, how do I do the pin assignment for the
fpga? Clarification of these basic doubts would do a world of good
to my project.
Thanks a lot.
Regards,
Kuntal M.
Regardling build code for the FPGA, I think that the fastest path to
enlightenment would be to spend some time with the Quartus II manuals,
and to look at the project files in usrp/toplevel/usrp_std
Regarding verilog programming in general, please try google. There
are many many tutorials on the web.
Eric