Reducing clock feedthrough

Hi there,

I’m running into clock feedthrough interference at the 5th harmonic of
the USRP oscillator (1088MHz) leaking into the DBSRX board. I found
Matt’s advice to Eric C. to change DBSRX C261 and C262 to 4700pF
to filter the clock more aggressively, and while this helped a little, I
still have clock noise that peaks at 40dB above the noise floor (decim.
8, gain 36). Additionally, the noise is strong enough that I’m picking
up intermod at 1084MHz and 1092MHz when the gain is pushed above 26.
Obviously this is reducing my receiver sensitivity. Two questions:

  • Where is the 4MHz modulation coming from that creates intermod at 1084
    and 1092?
  • How can I reduce clock feedthrough at 1088? Saying “use a different
    clock speed” is a perfectly viable answer, though I was hoping for a way
    to do it with the stock 64MHz oscillator as it really simplifies things.
    “Use an LNA” is another alternative, but since the LNA on the DBSRX is
    perfectly good it’d simplify things, again, to use a single amp.